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參數資料
| 型號： | ADMC328 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 28-Lead ROM-Based DSP Motor Controller(28腳含ROM、數字信號處理的的馬達控制器) |
| 中文描述： | 28 - ROM的鉛基于DSP的電機控制器（28腳含光盤，數字信號處理的的馬達控制器） |
| 文件頁數： | 17/36頁 |
| 文件大?。?/td> | 470K |
| 代理商： | ADMC328 |
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PRELIMINARY TECHNICAL DATA ADMC328
–17–
REV. A
tion illustrated in Figure 9, the appropriate value for the
PWMSEG register is 0x00A7. In ECM operation, each
inverter leg is disabled for certain periods of time, so that
the PWMSEG register is changed based upon the position
of the rotor shaft (motor commutation).
AH
AL
BH
BL
CH
CL
PWMTM
PW MTM
PW MCHA
= PW MCHB
PW MCHA
= PW MCHB
2
3
PWMDT
2
3
PWMDT
Figure 9. An example of PWM signals suitable for ECM
control. PWMCHA = PWMCHB, BH/BL are a crossover
pair. AL, BH, CH and CL outputs are disabled. Operation
is in single update mode.
Gate Drive Unit: PWMGATE Register
T he gate drive unit of the PWM controller adds features
which simplify the design of isolated gate drive circuits for
PWM inverters. If a transformer coupled power device gate
drive amplifier is used, the active PWM signal must be
chopped at a high frequency. T he PWMGAT E register
allows the programming of this high frequency chopping
mode. T he chopped active PWM signals may be required
for the high-side drivers only, for the low-side drivers only,
or for both the high-side and low-side switches. T herefore,
independent control of this mode for both high and low-
side switches is included with two separate control bits in
the PWMGAT E register.
T ypical PWM output signals with high-frequency chopping
enabled on both high-side and low-side signals are shown
in Figure 10. Chopping of the high-side PWM outputs
(AH, BH and CH) is enabled by setting bit 8 of the
PWMGAT E register. Chopping of the low-side PWM
outputs (AL, BL and CL) is enabled by setting bit 9 of the
PWMGAT E register. T he high chopping frequency is con-
trolled by the 8-bit word (GDCLK ) written to bits 0 to 7 of
the PWMGAT E register. T he period and the frequency of
this high frequency carrier are:
T
CHOP
= [ 4
3
( GDCLK + 1 )]
3
t
CK
f
C H O P
=
f
C L K O U T
[
4
×
(
G D C L K
+
1
)]
T he GDCLK value may range from 0 to 255, correspond-
ing to a programmable chopping frequency rate from 19.5
kHz to 5 MHz for a 20 MHz CLK OUT rate. T he gate
drive features must be programmed before operation of the
PWM controller and typically are not changed during nor-
mal operation of the PWM controller. Following a reset, by
default, all bits of the PWMGAT E register are cleared so
that high frequency chopping is disabled.
PWMTM
PW MTM
[4
3
(GDCLK+1)
3
t
CK
]
2
3
PWMDT
2
3
PWMDT
PWMCHA
PWMCHA
Figure 10. Typical PWM signals with high-frequency gate
chopping enabled on both high-side and low-side
switches (GDCLK is the integer equivalent of the value in
bits 0 to 7 of the PWMGATE register.)
PWM Shutdown
In the event of external fault conditions, it is essential that
the PWM system be instantaneously shutdown. T wo meth-
ods of sensing a fault condition are provided by the
ADMC328. For the first method, a falling edge on the
PWMTRIP
pin initiates an instantaneous, asynchronous
(independent of DSP clock) shutdown of he PWM control-
ler. T his places all six PWM outputs in the OFF state,
disables the PWMSYNC pulse and associated interrupt
signal and generates a
PWMTRIP
interrupt signal. T he
PWMTRIP
pin has an internal pull-down resistor so
that even if the pin becomes disconnected, the PWM
register will be disabled. T he state of the
PWMTRIP
pin
can be read from bit 0 of the SYST AT register.
T he second method for detecting a fault condition is through
the I
SENSE
pin in the analog block of the ADMC328. T he
I
SENSE
pin monitors the feedback signals from a dc bus
current sensing resistor which represents the total current
in the motor. When the voltage of I
SENSE
goes below I
SENSE
trip threshold,
PWMTRIP
will be internally pulled low.
T he negative edge of the internal
PWMTRIP
will generate
a shutdown in the same manner as a negative edge on
pin
PWMTRIP.
T his fault condition corresponds to a
5.5 ampere trip current in a 0.10 ohm sense resistor in
the dc power bus.
It is possible through software to initiate a PWM shutdown
by writing to the 1-bit read/write PWMSWT register
(0x2061). Writing to this bit generates a PWM shutdown
in a manner identical to the
PWMTRIP
or I
SENSE
pins.
Following a PWM shutdown, it is possible to determine if
the shutdown was generated from hardware or software by
reading the same PWMSWT register. Reading this register
also clears it.
T o restart the PWM after a fault condition is detected re-
quires clearing the fault and restarting the PWM. Clearing
the fault requires that
PWMTRIP
returns to a HI state and
I
SENSE
returns to a voltage greater than the I
SENSE
trip
threshold. After the fault has been cleared, the PWM can
be restarted by writing to registers PWMT M, PWMCHA,
PWMCHB, and PWMCHC. After the fault is cleared and
the PWM registers are initialized, internal timing of the
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