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參數(shù)資料
| 型號： | ADF4150HVBCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FRACTION-N FREQ SYNTH 32LFCSP |
| 標準包裝： | 1,500 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | CMOS |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 3GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-WQ（5x5） |
| 包裝： | 帶卷 (TR) |
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ADF4150HV
Rev. 0 | Page 11 of 28
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 14. The SW1 and
SW2 switches are normally closed. The SW3 switch is normally
open. When power-down is initiated, SW3 is closed, and SW1
and SW2 are opened. In this way, no loading of the REFIN pin
occurs during power-down.
BUFFER
TO R COUNTER
REFIN
100k
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
09
05
8-
0
10
Figure 14. Reference Input Stage
RF N DIVIDER
The RF N divider allows a division ratio in the PLL feedback
path. The division ratio is determined by the INT, FRAC, and
MOD values, which build up this divider (see Figure 15).
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRAC
VALUE
MOD
VALUE
INT
VALUE
RF N DIVIDER
N = INT + FRAC/MOD
FROM
VCO OUTPUT/
OUTPUT DIVIDERS
TO PFD
N COUNTER
09
05
8-
0
11
Figure 15. RF N Divider
INT, FRAC, MOD, and R Counter Relationship
The INT, FRAC, and MOD values, in conjunction with the
R counter, make it possible to generate output frequencies that
are spaced by fractions of the PFD frequency. For more informa-
tion, see the RF Synthesizer—A Worked Example section.
The RF VCO frequency (RFOUT) equation is
RFOUT = (fPFD/RF Divider) × [INT + (FRAC/MOD)]
(1)
where:
RFOUT is the output frequency of the external voltage controlled
oscillator (VCO).
RF Divider is the output divider that divides down the VCO
frequency.
INT is the preset divide ratio of the binary 16-bit counter (23 to
32,767 for the 4/5 prescaler, 75 to 65,535 for the 8/9 prescaler).
FRAC is the numerator of the fractional division (0 to MOD 1).
MOD is the preset fractional modulus (2 to 4095).
The PFD frequency (fPFD) equation is
fPFD = REFIN × [(1 + D)/(R × (1 + T))]
(2)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit.
R is the preset divide ratio of the binary 10-bit programmable
reference counter (1 to 1023).
T is the REFIN divide-by-2 bit (0 or 1).
Integer-N Mode
If FRAC = 0 and the DB8 (LDF) bit in Register 2 is set to 1,
the synthesizer operates in integer-N mode. The DB8 bit in
Register 2 should be set to 1 for integer-N digital lock detect.
R Counter
The 10-bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock
to the PFD. Division ratios from 1 to 1023 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND HIGH
VOLTAGE CHARGE PUMP
The phase frequency detector (PFD) takes inputs from the
R counter and N counter and produces an output proportional
to the phase and frequency difference between them. Figure 16
is a simplified schematic of the phase frequency detector.
U3
CLR2
Q2
D2
U2
DOWN
UP
HIGH
CPOUT
–IN
+IN
CHARGE
PUMP
DELAY
CLR1
Q1
D1
U1
09
05
8-
01
2
Figure 16. PFD Simplified Schematic
The PFD includes a delay element that sets the width of the
antibacklash pulse to 4.2 ns. This pulse ensures that there is
no dead zone in the PFD transfer function and provides a
consistent reference spur level.
The high voltage charge pump is designed on an Analog
Devices, Inc., proprietary high voltage process and allows the
charge pump to output voltages as high as 29 V when powered
by a 30 V supply. The high voltage charge pump removes the
need for active filtering when interfacing to a high voltage VCO.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4151 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fractional-N/Integer-N PLL Synthesizer |
| ADF4151BCPZ | 功能描述:IC PLL FREQ SYNTHESIZER 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4151BCPZ-RL7 | 功能描述:IC FRACTION-N FREQ SYNTH 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4152HVBCPZ | 功能描述:IC FRACTION-N FREQ SYNTH 32LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:* PLL:是 輸入:CMOS 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:2:2 差分 - 輸入:輸出:是/無 頻率 - 最大值:5GHz 分頻器/倍頻器:是/是 電壓 - 電源:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤，CSP 供應商器件封裝:32-LFCSP-VQ（5x5） 標準包裝:1 |
| ADF4152HVBCPZ-RL7 | 功能描述:IC FRACTION-N FREQ SYNTH 32LFCSP 制造商:analog devices inc. 系列:- 包裝:剪切帶（CT） 零件狀態(tài):在售 類型:* PLL:是 輸入:CMOS 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:2:2 差分 - 輸入:輸出:是/無 頻率 - 最大值:5GHz 分頻器/倍頻器:是/是 電壓 - 電源:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤，CSP 供應商器件封裝:32-LFCSP-VQ（5x5） 標準包裝:1 |
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