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參數(shù)資料
| 型號(hào)： | ADF4150HVBCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/28頁 |
| 文件大小： | 0K |
| 描述： | IC FRACTION-N FREQ SYNTH 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | CMOS |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 3GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-WQ（5x5） |
| 包裝： | 帶卷 (TR) |
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ADF4150HV
Rev. 0 | Page 12 of 28
MUXOUT AND LOCK DETECT
The multiplexer output on the ADF4150HV allows the user to
access various internal points on the chip. The state of MUXOUT is
controlled by the M3, M2, and M1 bits in Register 2 (see Figure 22).
Figure 17 shows the MUXOUT section in block diagram form.
GND
DVDD
CONTROL
MUX
MUXOUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
GND
RESERVED
THREE-STATE-OUTPUT
DVDD
R COUNTER INPUT
09
05
8-
01
3
Figure 17. MUXOUT Schematic
INPUT SHIFT REGISTERS
The ADF4150HV digital section includes a 10-bit RF R counter,
a 16-bit RF N counter, a 12-bit FRAC counter, and a 12-bit
modulus counter. Data is clocked into the 32-bit shift register
on each rising edge of CLK. The data is clocked in MSB first.
Data is transferred from the shift register to one of six latches
on the rising edge of LE. The destination latch is determined by
the state of the three control bits (C3, C2, and C1) in the shift
register. As shown in Figure 2, the control bits are the three LSBs:
DB2, DB1, and DB0. The truth table for these bits is shown in
Table 6. Figure 19 summarizes how the latches are programmed.
Table 6. Truth Table for C3, C2, and C1 Control Bits
Control Bits
Register
C3
C2
C1
0
Register 0 (R0)
0
1
Register 1 (R1)
0
1
0
Register 2 (R2)
0
1
Register 3 (R3)
1
0
Register 4 (R4)
1
0
1
Register 5 (R5)
PROGRAM MODES
modes are set up in the ADF4150HV.
The following settings in the ADF4150HV are double buffered:
phase value, modulus value, reference doubler, reference divide-
by-2, R counter value, and charge pump current setting. Before
the part uses a new value for any double-buffered setting, the
following two events must occur:
1.
The new value is latched into the device by writing to the
appropriate register.
2.
A new write is performed on Register 0 (R0).
For example, any time that the modulus value is updated,
Register 0 (R0) must be written to, to ensure that the modulus
value is loaded correctly. The divider select value in Register 4
(R4) is also double buffered, but only if the DB13 bit of
Register 2 (R2) is high.
OUTPUT STAGE
to the collectors of an NPN differential pair driven by buffered
outputs of the VCO, as shown in Figure 18. To allow the user to
optimize the power dissipation vs. output power requirements,
the tail current of the differential pair is programmable using
Bits[DB4:DB3] in Register 4 (R4). Four current levels can be set.
These levels give output power levels of 4 dBm, 1 dBm, +2 dBm,
and +5 dBm, respectively, using a 50 Ω resistor to AVDD and ac
coupling into a 50 Ω load. Alternatively, both outputs can be
combined in a 1 + 1:1 transformer or a 180° microstrip coupler
(see the Output Matching section). If the outputs are used
individually, the optimum output stage consists of a shunt
inductor to AVDD.
VCO
RFOUT+RFOUT–
09
05
8
-01
4
BUFFER/
DIVIDE-BY-1/-2/-4/-8/-16
Figure 18. Output Stage
Another feature of the ADF4150HV is that the supply current to
the RF output stage can be shut down until the part achieves lock,
as measured by the digital lock detect circuitry. This feature is
enabled by the mute-till-lock detect (MTLD) bit in Register 4 (R4).
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| ADF4151 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fractional-N/Integer-N PLL Synthesizer |
| ADF4151BCPZ | 功能描述:IC PLL FREQ SYNTHESIZER 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4151BCPZ-RL7 | 功能描述:IC FRACTION-N FREQ SYNTH 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4152HVBCPZ | 功能描述:IC FRACTION-N FREQ SYNTH 32LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:* PLL:是 輸入:CMOS 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:2:2 差分 - 輸入:輸出:是/無 頻率 - 最大值:5GHz 分頻器/倍頻器:是/是 電壓 - 電源:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-VQ（5x5） 標(biāo)準(zhǔn)包裝:1 |
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