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| 型號： | ADF4150HVBCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FRACTION-N FREQ SYNTH 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | CMOS |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 3GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-WQ（5x5） |
| 包裝： | 帶卷 (TR) |
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ADF4150HV
Rev. 0 | Page 18 of 28
Reference Doubler
Setting the DB25 bit to 0 disables the doubler and feeds the
REFIN signal directly into the 10-bit R counter. Setting this bit to
1 multiplies the REFIN frequency by a factor of 2 before feeding
it into the 10-bit R counter. When the doubler is disabled, the
REFIN falling edge is the active edge at the PFD input to the
fractional synthesizer. When the doubler is enabled, both the
rising and falling edges of REFIN become active edges at the
PFD input.
When the doubler is enabled and the low spur mode is chosen,
the in-band phase noise performance is sensitive to the REFIN duty
cycle. The phase noise degradation can be as much as 5 dB for
REFIN duty cycles outside a 45% to 55% range. The phase noise
is insensitive to the REFIN duty cycle in the low noise mode and
when the doubler is disabled.
The maximum allowable REFIN frequency when the doubler is
enabled is 30 MHz.
RDIV2
Setting the DB24 bit to 1 inserts a divide-by-2 toggle flip-flop
between the R counter and the PFD. This function allows a 50%
duty cycle signal to appear at the PFD input, which is necessary
when the charge pump boost mode is enabled (see the Boost
Enable section).
10-Bit R Counter
The 10-bit R counter (Bits[DB23:DB14]) allows the input
reference frequency (REFIN) to be divided down to produce the
reference clock to the PFD. Division ratios from 1 to 1023 are
allowed.
Double Buffer
The DB13 bit enables or disables double buffering of
Bits[DB22:DB20] in Register 4. For information about how
double buffering works, see the Program Modes section.
Charge Pump Current Setting
Bits[DB11:DB9] set the charge pump current. This value
should be set to the charge pump current that the loop filter
is designed with (see Figure 22).
Lock Detect Function (LDF)
The DB8 bit configures the lock detect function (LDF). The LDF
controls the number of PFD cycles monitored by the lock detect
circuit to ascertain whether lock has been achieved. When DB8
is set to 0, the number of PFD cycles monitored is 40. When
DB8 is set to 1, the number of PFD cycles monitored is 5. It is
recommended that the DB8 bit be set to 0 for fractional-N mode
and 1 for integer-N mode.
Lock Detect Precision (LDP)
The lock detect precision bit (Bit DB7) sets the comparison
window in the lock detect circuit. When DB7 is set to 0, the
comparison window is 10 ns; when DB7 is set to 1, the window
is 6 ns. The lock detect circuit goes high when n consecutive
PFD cycles are less than the comparison window value; n is set
by the LDF bit (DB8). For example, with DB8 = 0 and DB7 = 0,
40 consecutive PFD cycles of 10 ns or less must occur before
digital lock detect goes high. The recommended settings for
Bits[DB8:DB7] are listed in Table 7.
Table 7. Recommended LDF and LDP Bit Settings
Mode
DB8 (LDF)
DB7 (LDP)
Integer-N
1
Fractional-N, Low Noise Mode
0
1
Fractional-N, Low Spur Mode
0
Power-Down (PD)
The DB5 bit provides the programmable power-down mode.
Setting this bit to 1 performs a power-down. Setting this bit to 0
returns the synthesizer to normal operation. In software power-
down mode, the part retains all information in its registers. The
register contents are lost only if the supply voltages are removed.
When power-down is activated, the following events occur:
Synthesizer counters are forced to their load state
conditions.
Charge pump is forced into three-state mode.
Digital lock detect circuitry is reset.
RFOUT buffers are disabled.
Input registers remain active and capable of loading
and latching data.
Charge Pump Three-State
Setting the DB4 bit to 1 puts the charge pump into three-state
mode. This bit should be set to 0 for normal operation.
Counter Reset
The DB3 bit is the reset bit for the R counter and the N counter
of the ADF4150HV. When this bit is set to 1, the RF synthesizer
N counter and R counter are held in reset. For normal opera-
tion, this bit should be set to 0.
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| ADF4151 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fractional-N/Integer-N PLL Synthesizer |
| ADF4151BCPZ | 功能描述:IC PLL FREQ SYNTHESIZER 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4151BCPZ-RL7 | 功能描述:IC FRACTION-N FREQ SYNTH 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4152HVBCPZ | 功能描述:IC FRACTION-N FREQ SYNTH 32LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:* PLL:是 輸入:CMOS 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:2:2 差分 - 輸入:輸出:是/無 頻率 - 最大值:5GHz 分頻器/倍頻器:是/是 電壓 - 電源:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-VQ（5x5） 標(biāo)準(zhǔn)包裝:1 |
| ADF4152HVBCPZ-RL7 | 功能描述:IC FRACTION-N FREQ SYNTH 32LFCSP 制造商:analog devices inc. 系列:- 包裝:剪切帶（CT） 零件狀態(tài):在售 類型:* PLL:是 輸入:CMOS 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:2:2 差分 - 輸入:輸出:是/無 頻率 - 最大值:5GHz 分頻器/倍頻器:是/是 電壓 - 電源:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-VQ（5x5） 標(biāo)準(zhǔn)包裝:1 |
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