參數(shù)資料
型號: ADAU1781BCPZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 87/92頁
文件大?。?/td> 0K
描述: IC SIGMADSP CODEC LN 32LFCSP
標準包裝: 1,500
系列: SigmaDSP®
類型: 立體聲音頻
數(shù)據(jù)接口: I²C,串行,SPI?
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
S/N 比,標準 ADC / DAC (db): 100 / 105(差分),100 / 103(單端)
動態(tài)范圍,標準 ADC / DAC (db): 99.2 / 105(差分),99.2 / 103(單端)
電壓 - 電源,模擬: 1.8 V ~ 3.65 V
電壓 - 電源,數(shù)字: 1.63 V ~ 3.65 V
工作溫度: -25°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ
包裝: 帶卷 (TR)
ADAU1781
Rev. B | Page 88 of 92
Register 16628 (0x40F4), Serial Data/GPIO Pin
Configuration
Bits[3:0], GPIO[0:3]
The serial data/GPIO pin configuration register controls the
functionality of the serial data port pins. If the bits in this
register are set to 1, then the GPIO[0:3] pins become GPIO
interfaces to the SigmaDSP core. If these bits are set to 0, they
remain LRCLK, BCLK, or serial port data pins, respectively.
Register 16630 (0x40F6), SigmaDSP Core Run
Bit 0, SigmaDSP Core Run
This bit, in conjunction with the SigmaDSP core frame rate,
initiates audio processing in the SigmaDSP core. When this bit is
enabled, the program counter begins to increment when a new
frame of audio data is input to the SigmaDSP core. When this bit is
disabled, the SigmaDSP core goes into standby mode.
Before going into standby mode, the following sequence must
be performed:
1. Set the SigmaDSP core frame rate in Register 16619 to
0x7F (none).
2. Wait 3 ms.
3. Set the SigmaDSP core run bit in Register 16630 to 0x00.
When reenabling the SigmaDSP core run bit, the following
sequence must be followed:
1. Set the SigmaDSP core frame rate in Register 16619 to an
appropriate value.
2. Set the SigmaDSP core run bit in Register 16630 to 0x01.
Register 16632 (0x40F8), Serial Port Sampling Rate
Bits[2:0], Serial Port Control Sampling Rate
These bits set the serial port sampling rate as a function of the
audio sampling rate, fS. In most applications, the serial port
sampling rate, SigmaDSP core sampling rate, and ADC and
DAC sampling rates should be equal.
Table 80. Serial Data/GPIO Pin Configuration Register
Bits
Description
Default
[7:4]
Reserved
3
GPIO0
0
0: LRCLK
1: GPIO enabled
2
GPIO1
0
0: BCLK
1: GPIO enabled
1
GPIO2
0
0: serial data output
1: GPIO enabled
0
GPIO3
0
0: serial data input
1: GPIO enabled
Table 81. SigmaDSP Core Run Register
Bits
Description
Default
[7:1]
Reserved
0
SigmaDSP core run
0
0: SigmaDSP core standby
1: run the SigmaDSP core
Table 82. Serial Port Sampling Rate Register
Bits
Description
Default
[7:3]
Reserved
[2:0]
Serial port control sampling rate
000
000: fS/1 (48 kHz)
001: fS/6 (8 kHz)
010: fS/4 (12 kHz)
011: fS/3 (16 kHz)
100: fS/2 (24 kHz)
101: fS/1.5 (32 kHz)
110: fS/0.5 (96 kHz)
111: reserved
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