參數(shù)資料
型號： ADAU1781BCPZ-RL7
廠商： Analog Devices Inc
文件頁數(shù)： 46/92頁
文件大?。?/td> 0K
描述： IC SIGMADSP CODEC LN 32LFCSP
標(biāo)準(zhǔn)包裝： 1,500
系列： SigmaDSP®
類型： 立體聲音頻
數(shù)據(jù)接口： I²C，串行，SPI?
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 無
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 100 / 105（差分），100 / 103（單端）
動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 99.2 / 105（差分），99.2 / 103（單端）
電壓 - 電源，模擬： 1.8 V ~ 3.65 V
電壓 - 電源，數(shù)字： 1.63 V ~ 3.65 V
工作溫度： -25°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ
包裝： 帶卷 (TR)
ADAU1781
Rev. B | Page 50 of 92
Register 16385 (0x4001), Regulator Control
Bits[2:1], Regulator Output Level
These bits set the regulated voltage output for the digital core,
DVDDOUT. After the initialization sequence has completed,
the regulator output is set to 1.4 V. The recommended regulator
output level when the device begins to process audio is 1.5 V.
Therefore, this register should be set to 1.5 V when the
SigmaDSP core is being configured.
Register 16386 (0x4002), PLL Control
This is a 48-bit register that must be written to in a single burst
write. PLL operating parameters are used to scale the MCLK
input to the desired clock core in order to obtain an appropriate
PLL clock (PLL output frequency). The PLL can be configured
for either fractional or integer-N type MCLK inputs.
Bits[47:40], Denominator MSB
Byte 1, M[15:8] of the denominator (M) for fractional part of feed-
back divider. This is concatenated with Denominator LSB, M[7:0].
Bits[39:32], Denominator LSB
Byte 0, M[7:0] of the denominator (M) for fractional part of feed-
back divider. This is concatenated with Denominator MSB, M[15:8].
Bits[31:24], Numerator MSB
Byte 1, N[15:8] of the numerator (N) for fractional part of the feed-
back divider. This is concatenated with Numerator LSB, N[7:0].
Bits[23:16], Numerator LSB
Byte 0, N[7:0] of the numerator (N) for fractional part of the feed-
back divider. This is concatenated with Numerator MSB, N[15:8].
Bits[14:11], Integer
Integer (R) parameter used in both integer-N and fractional
PLL operation. This value must be between 2 and 8.
Bits[10:9], Input Divider
The input divider (X) divides the input clock to offer a wider
range of input clocks.
Bit 8, PLL Type
This selects the type of PLL operation, fractional or integer-N.
Fractional Type PLL
Fractional type MCLK inputs are scaled to the corresponding
desired core clock input using the parameters outlined in Table 39
and Table 40 as examples of typical base sampling frequencies
(44.1 kHz and 48 kHz). A numerical-controlled oscillator is
used to divide the PLL_CLK by a mixed number given by the
addition of the integer part (R) and fractional part (N/M).
For example, if the MCLK is 12 MHz, the required clock is
12.288 MHz, and fS is 48 kHz, then the PLL clock is 49.152 MHz
because PLL clock is always 1024 × fS; therefore,
PLL Clock/MCLK = 4.096 = 4 + (12/125) = R + (N/M)
In this case, the input divider is X = 1.
This allows the MCLK input to emulate the desired required clock
and output a 49.152 MHz PLL clock. Figure 29 shows how the PLL
uses the parameters to emulate the required 12.288 MHz clock.
Integer-N Type PLL
Integer-N type MCLK inputs are any integer multiple of the
desired core clock. The fractional part (N/M) is 0; however, the
PLL type bit must be set for integer-N.
Bit 1, PLL Lock
The PLL lock bit is a read-only bit. Reading a 1 from this bit
indicates that the PLL has locked to the input master clock.
Bit 0, PLL Enable
This bit enables the PLL.
Table 37. Regulator Control Register
Bits
Description
Default
[7:3]
Reserved
[2:1]
Regulator output level
01
00: 1.5 V
01: 1.4 V
10: 1.6 V
11: 1.7 V
0
Reserved
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