參數(shù)資料
型號(hào)： ADAU1781BCPZ-RL7
廠商： Analog Devices Inc
文件頁數(shù)： 36/92頁
文件大?。?/td> 0K
描述： IC SIGMADSP CODEC LN 32LFCSP
標(biāo)準(zhǔn)包裝： 1,500
系列： SigmaDSP®
類型： 立體聲音頻
數(shù)據(jù)接口： I²C，串行，SPI?
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 無
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 100 / 105（差分），100 / 103（單端）
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 99.2 / 105（差分），99.2 / 103（單端）
電壓 - 電源，模擬： 1.8 V ~ 3.65 V
電壓 - 電源，數(shù)字： 1.63 V ~ 3.65 V
工作溫度： -25°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ
包裝： 帶卷 (TR)
ADAU1781
Rev. B| Page 41 of 92
DSP CORE
SIGNAL PROCESSING
The ADAU1781 is designed to provide all audio signal processing
functions commonly used in stereo or mono low power record
and playback systems. The signal processing flow is designed
using the SigmaStudio software, which allows graphical entry
and real-time control of all signal processing functions.
Many of the signal processing functions are coded using full,
56-bit, double-precision arithmetic data. The input and output
word lengths of the DSP core are 24 bits. Four extra headroom
bits are used in the processor to allow internal gains of up to
24 dB without clipping. Additional gains can be achieved by
initially scaling down the input signal in the DSP signal flow.
ARCHITECTURE
The DSP core consists of a simple 28-/56-bit multiply-accumulate
unit (MAC) with two sources: a data source and a coefficient
source. The data source can come from the data RAM, a ROM
table of commonly used constant values, or the audio inputs to
the core. The coefficient source can come from the parameter
RAM, a ROM table of commonly used constant values, or the
audio inputs to the core.
The two sources are multiplied in a 28-bit fixed-point multiplier,
and then the signal is input to the 56-bit adder; the result is usually
stored in one of three 56-bit accumulator registers. The accumu-
lators can be output from the core (in 28-bit format) or can
optionally be written back into the data or parameter RAMs.
PROGRAM COUNTER
The execution of instructions in the core is governed by a program
counter, which sequentially steps through the addresses of the
program RAM. The program counter starts every time a new
audio frame is clocked into the core. SigmaStudio inserts a
jump-to-start command at the end of every program. The
program counter increments sequentially until reaching this
command and then jumps to the program start address and
waits for the next audio frame to clock into the core.
FEATURES
The SigmaDSP core was designed specifically for audio processing
and therefore includes several features intended for maximizing
efficiency. These include hardware decibel conversion and audio-
specific ROM constants.
COEFFICIENT SOURCE
(PARAMETER RAM,
ROM CONSTANTS,
INPUTS, ...)
DATA OPERATIONS
(ACCUMULATORS (3), dB CONVERSION,
BIT OPERATORS, BIT SHIFTER, ...)
DATA SOURCE
(DATA RAM,
ROM CONSTANTS,
INPUTS, ...)
OUTPUTS
TRUNCATOR
56
28
56
08314-
200
Figure 51. Simplified DSP Core Architecture
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