參數(shù)資料
型號： ADAU1781BCPZ-RL7
廠商： Analog Devices Inc
文件頁數(shù)： 40/92頁
文件大?。?/td> 0K
描述： IC SIGMADSP CODEC LN 32LFCSP
標(biāo)準(zhǔn)包裝： 1,500
系列： SigmaDSP®
類型： 立體聲音頻
數(shù)據(jù)接口： I²C，串行，SPI?
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 無
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 100 / 105（差分），100 / 103（單端）
動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 99.2 / 105（差分），99.2 / 103（單端）
電壓 - 電源，模擬： 1.8 V ~ 3.65 V
電壓 - 電源，數(shù)字： 1.63 V ~ 3.65 V
工作溫度： -25°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ
包裝： 帶卷 (TR)
ADAU1781
Rev. B| Page 45 of 92
Table 28. Parameter RAM Read/Write Format (Single Address)
Byte 0
Byte 1
Byte 2
Byte 3
Bytes[4:6]
CHIP_ADR[6:0], R/W
PARAM_ADR[15:8]
PARAM_ADR[7:0]
0000, PARAM[27:24]
PARAM[23:0]
Table 29. Parameter RAM Block Read/Write Format (Burst Mode)
Byte 0
Byte 1
Byte 2
Byte 3
Bytes[4:6]
Bytes[7:10]
Bytes[11:14]
CHIP_ADR[6:0], R/W
PARAM_ADR[15:8]
PARAM_ADR[7:0]
0000, PARAM[27:24]
PARAM[23:0]
<—PARAM_ADR—>
PARAM_ADR + 1
PARAM_ADR + 2
Table 30. Program RAM Read/Write Format (Single Address)
Byte 0
Byte 1
Byte 2
Bytes[3:7]
CHIP_ADR[6:0], R/W
PROG_ADR[15:8]
PROG_ADR[7:0]
PROG[39:0]
Table 31. Program RAM Block Read/Write Format (Burst Mode)
Byte 0
Byte 1
Byte 2
Bytes[3:7]
Bytes[8:12]
Bytes[13:17]
CHIP_ADR[6:0], R/W
PROG_ADR[15:8]
PROG_ADR[7:0]
PROG[39:0]
PROG_ADR
PROG_ADR + 1
PROG_ADR + 2
SOFTWARE SAFELOAD
To update parameters in real time while avoiding pop and click
noises on the output, the ADAU1781 uses a software safeload
mechanism. The software safeload mechanism enables the
SigmaDSP core to load new parameters into RAM while
guaranteeing that the parameters are not in use. This prevents
an undesirable condition where an instruction may execute
with a mix of old and new parameters.
SigmaStudio sets up the necessary code and parameters auto-
matically for new projects. The safeload code, along with other
initialization code, fills the first 39 locations in program RAM.
The first eight parameter RAM locations (Address 0x0000 to
Address 0x0007) are configured by default in SigmaStudio as
described in Table 32.
Table 32. Software Safeload Parameter RAM Defaults
Address (Hex)
Function
0x0000
Modulo RAM size
0x0001
Safeload Data 1
0x0002
Safeload Data 2
0x0003
Safeload Data 3
0x0004
Safeload Data 4
0x0005
Safeload Data 5
0x0006
Safeload target address (offset of 1)
0x0007
Number of words to write/safeload trigger
Address 0x0000, which controls the modulo RAM size, is set
by SigmaStudio and is based on the dynamic address generator
mode of the project.
Parameter RAM Address 0x0001 to Address 0x0005 are the five
data slots for storing the data to be safeloaded. The safeload
parameter space contains five data slots by default because most
standard signal processing algorithms have five parameters or less.
Address 0x0006 is the target address in parameter RAM (with
an offset of 1). This designates the first address to be written.
If more than one word is written, the address increments auto-
matically for each data-word. Up to five sequential parameter
RAM locations can be updated with safeload during each audio
frame. The target address offset of 1 is used because the write
address is calculated relative to the address of the data, which
starts at Address 0x0001. Therefore, to update a parameter at
Address 0x000A, the target address is 0x0009.
Address 0x0007 designates the number of words to be written
into the parameter RAM during the safeload. A biquad filter
uses all five safeload data addresses. A simple mono gain cell
uses only one safeload data address. Writing to this address also
triggers the safeload write to occur in the next audio frame.
The safeload mechanism is software based and executes once
per audio frame. Therefore, system designers must take care
when designing the communication protocol. A delay equal to
or greater than the sampling period (the inverse of sampling
frequency) is required between each safeload write. A sample
rate of 48 kHz equates to a delay of at least 21 μs. If this delay
is not observed, the downloaded data is corrupted.
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