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參數(shù)資料
| 型號： | ADAU1461WBCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SIGMADSP 24BIT 96KHZ PLL 32 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SigmaDSP® |
| 類型： | 音頻處理器 |
| 應(yīng)用： | 車載音頻 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ |
| 包裝： | 托盤 |
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ADAU1461
Rev. 0 | Page 13 of 88
AG
ND
LIN
P
LI
N
RI
NP
RI
NN
RAUX
RO
UT
P
RO
UT
N
S
CL
/CCL
K
S
D
A/
CO
U
T
ADDR
1/
C
DAT
A
L
R
CL
K/
G
P
IO
3
BCL
K/
G
P
IO
2
DAC_S
DAT
A/
G
P
IO
0
ADC_S
DAT
A/
G
P
IO
1
DG
ND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
IOVDD
2
MCLK
3
ADDR0/CLATCH
4
JACKDET/MICIN
5
MICBIAS
6
LAUX
7
CM
8
AVDD
24 DVDDOUT
23 AVDD
22 AGND
21 MONOOUT
20 LHP
19 RHP
18 LOUTP
17 LOUTN
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
TOP VIEW
(Not to Scale)
ADAU1461
NOTES
1. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE
ADAU1461 GROUNDS. FOR INCREASED RELIABILITY OF THE
SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PAD BE SOLDERED TO THE
GROUND PLANE.
08
91
4-
0
07
Figure 7. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
IOVDD
PWR
Supply for Digital Input and Output Pins. The digital output pins are supplied from IOVDD,
which also sets the highest input voltage that should be seen on the digital input pins.
IOVDD should be set to 3.3 V. The current draw of this pin is variable because it is dependent
on the loads of the digital outputs. IOVDD should be decoupled to DGND with a 100 nF
capacitor and a 10 μF capacitor.
2
MCLK
D_IN
External Master Clock Input.
3
ADDR0/CLATCH
D_IN
I2C Address Bit 0 (ADDR0).
SPI Latch Signal (CLATCH). Must go low at the beginning of an SPI transaction and high at the
end of a transaction. Each SPI transaction can take a different number of CCLKs to complete,
depending on the address and read/write bit that are sent at the beginning of the SPI
transaction.
4
JACKDET/MICIN
D_IN
Detect Insertion/Removal of Headphone Plug (JACKDET).
Digital Microphone Stereo Input (MICIN).
5
MICBIAS
A_OUT
Bias Voltage for Electret Microphone.
6
LAUX
A_IN
Left Channel Single-Ended Auxiliary Input. Biased at AVDD/2.
7
CM
A_OUT
AVDD/2 V Common-Mode Reference. A 10 μF to 47 μF standard decoupling capacitor should
be connected between this pin and AGND to reduce crosstalk between the ADCs and DACs.
This pin can be used to bias external analog circuits, as long as they are not drawing current
from CM (for example, the noninverting input of an op amp).
8
AVDD
PWR
3.3 V Analog Supply for DAC and Microphone Bias. This pin should be decoupled locally to
AGND with a 100 nF capacitor.
9
AGND
PWR
Analog Ground. The AGND and DGND pins can be tied together on a common ground plane.
AGND should be decoupled locally to AVDD with a 100 nF capacitor.
10
LINP
A_IN
Left Channel Noninverting Input or Single-Ended Input 0. Biased at AVDD/2.
11
LINN
A_IN
Left Channel Inverting Input or Single-Ended Input 1. Biased at AVDD/2.
12
RINP
A_IN
Right Channel Noninverting Input or Single-Ended Input 2. Biased at AVDD/2.
13
RINN
A_IN
Right Channel Inverting Input or Single-Ended Input 3. Biased at AVDD/2.
14
RAUX
A_IN
Right Channel Single-Ended Auxiliary Input. Biased at AVDD/2.
15
ROUTP
A_OUT
Right Line Output, Positive. Biased at AVDD/2.
16
ROUTN
A_OUT
Right Line Output, Negative. Biased at AVDD/2.
17
LOUTN
A_OUT
Left Line Output, Negative. Biased at AVDD/2.
18
LOUTP
A_OUT
Left Line Output, Positive. Biased at AVDD/2.
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