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參數(shù)資料
| 型號(hào)： | ADAU1461WBCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SIGMADSP 24BIT 96KHZ PLL 32 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SigmaDSP® |
| 類型： | 音頻處理器 |
| 應(yīng)用： | 車載音頻 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ |
| 包裝： | 托盤 |
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ADAU1461
Rev. 0 | Page 34 of 88
HEADPHONE OUTPUT
The LHP and RHP pins can be driven by either a line output
driver or a headphone driver by setting the HPMODE bit in
Register R30 (playback headphone right volume control register,
Address 0x4024). The headphone outputs can drive a load of at
least 16 Ω.
Separate volume controls for the left and right channels range
from 57 dB to +6 dB. Slew can be applied to all the playback
volume controls using the ASLEW[1:0] bits in Register R34
(playback pop/click suppression register, Address 0x4028).
Capless Headphone Configuration
The headphone outputs can be configured in a capless output
configuration with the MONOOUT pin used as a dc virtual
ground reference. Figure 45 depicts a typical playback path in
a capless headphone configuration. Table 18 lists the register
settings for this configuration. As shown in this table, the
MONOOUT pin outputs common mode (AVDD/2), which
is used as the virtual headphone reference.
LHP
MONOOUT
MIXER 3
LEFT
DAC
MX3LM
LHPVOL[5:0]
MX3EN
RHP
MIXER 4
RHPVOL[5:0]
RIGHT
DAC
MX4RM
MX4EN
MIXER 7
MX7[1:0]
MONOM
MOMODE
MX7EN
08
91
4-
0
6
2
Figure 45. Capless Headphone Configuration Diagram
Table 18. Capless Headphone Register Settings
Register
Bit Name
Setting
R36
DACEN[1:0]
11 = both DACs on
R22
MX3EN
1 = enable Mixer 3
MX3LM
1 = unmute left DAC input
R24
MX4EN
1 = enable Mixer 4
MX4RM
1 = unmute right DAC input
R28
MX7EN
1 = enable Mixer 7
MX7[1:0]
00 = common-mode output
R33
MONOM
1 = unmute mono output
MOMODE
1 = headphone output
R29
LHPVOL[5:0]
Desired volume for LHP output
LHPM
1 = unmute left headphone output
R30
HPMODE
1 = headphone output
RHPVOL[5:0]
Desired volume for RHP output
RHPM
1 = unmute right headphone output
Headphone Output Power-Up/Power-Down Sequencing
To prevent pops when turning on the headphone outputs, the
user must wait at least 4 ms to unmute these outputs after
enabling the headphone output with the HPMODE bit. This is
because of an internal capacitor that must charge before these
headphone power-up/power-down sequencing.
For capless headphones, configure the MONOOUT pin before
unmuting the headphone outputs.
USER
DEFINED
4ms
HPMODE
1 = HEADPHONE
INTERNAL
PRECHARGE
RHPM AND LHPM
1 = UNMUTE
08
91
4-
04
6
Figure 46. Headphone Output Power-Up Timing
USER DEFINED
08
91
4-
04
7
HPMODE
0 = LINE OUTPUT
RHPM AND LHPM
0 = MUTE
Figure 47. Headphone Output Power-Down Timing
Ground-Centered Headphone Configuration
The headphone outputs can also be configured as ground-
centered outputs by placing coupling capacitors on the LHP
and RHP pins. Ground-centered headphones should use the
AGND pin as the ground reference.
When the headphone outputs are configured in this manner,
the capacitors create a high-pass filter on the outputs. The
corner frequency of this filter, at which point its attenuation
is 3 dB, is calculated by the following formula:
f3dB = 1/(2π × R × C)
where:
C is the capacitor value.
R is the impedance of the headphones.
For a typical headphone impedance of 16 Ω and a 47 μF
capacitor, the corner frequency is 211 Hz.
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| ADAU1461WBCPZ-R7 | 功能描述:IC SIGMADSP 24BIT 96KHZ PLL 32 RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
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| ADAU1462WBCPZ150RL | 功能描述:32BIT SIGMADSP AUDIO 16K/48K 制造商:analog devices inc. 系列:* 包裝:帶卷（TR） 零件狀態(tài):在售 安裝類型:表面貼裝 封裝/外殼:72-VFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:72-LFCSP（10x10） 標(biāo)準(zhǔn)包裝:2,000 |
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