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| 型號(hào)： | ADAU1373BCBZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 261/296頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CODEC LP CLASS G HP 81WLCSP |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類(lèi)型： | 音頻編解碼器 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 1 / 2 |
| 三角積分調(diào)變： | 是 |
| S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： | 96 / 96 |
| 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 96 / 96 |
| 電壓 - 電源，模擬： | 1.62 V ~ 1.98 V |
| 電壓 - 電源，數(shù)字： | 1.08 V ~ 1.98 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 81-UFBGA，WLCSP |
| 供應(yīng)商設(shè)備封裝： | 81-WLCSP（4.05x3.82） |
| 包裝： | 帶卷 (TR) |
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ADAU1373
Rev. 0 | Page 67 of 296
DIGITAL AUTOMATIC LEVEL CONTROL (ALC)
The automatic level control (ALC) provides continuous
adjustment of the input PGA in response to the rms amplitude
of the input signal to maintain it at a constant level, which is
defined by the ALCREF bits (Register 0xC4, Bits[3:0]). A digital
peak detector monitors the input signal amplitude and limits it
to the register-defined threshold level, using the ALCLVL bits
(Register 0xC4, Bits[7:4]).
The ALC provides control over analog PGA and digital PGA,
which can be selected individually or together.
To reduce the gain during the silent portion of the speech or
music signal, the ALC provides a noise gate that can be oper-
ated in four different modes, as defined by the NGMODE bits
(Register 0xC8, Bits[5:4]).
Noise Gate Mode 1. Maintains the gain at the level it was
before the ALC entered into noise gate mode.
Noise Gate Mode 2. Sets the PGA gain to 0 dB.
Noise Gate Mode 3. Mutes the ALC output.
Noise Gate Mode 4. Noise gate function is disabled.
The ALC can be enabled or disabled for the left or right channel
or for both channels via the ALCEN bits (Register 0xC8, Bits[3:2]).
If the rms value of the signal falls below the ALC target threshold
(as defined by the ALCREF bits), the ALC increases the gain of
the PGA at the rate set by the ALCREC bits (Register 0xC3,
Bits[3:0]). If the signal is above the threshold, the ALC reduces
the gain of the PGA at a rate that is set by the ALCATT bits
(Register 0xC3, Bits[7:4]).
Because the dc offset introduced by the analog circuits greatly
influences ALC operation, it is recommended that the HPF
included in the ALC block be enabled when the ALC is enabled.
Peak Limiter Level
To prevent clipping during high level signals, the ALC circuit
includes a limiter function. If the ALC input signal exceeds the
peak level threshold (as defined by the ALCLVL bits), the PGA
gain is ramped down as per the attack time set by the ALCATT
bits until the signal level falls below that threshold. This function
is automatically enabled when the ALC is enabled. The peak
limiter level can be set using the ALCLVL bits. The level can be
set from 22.5 dBFs to 0 dBFS in 16 steps.
ALC Target level
When the signal level is below the peak limiter threshold, the
ALC attempts to maintain a constant signal level by increasing
or decreasing the gain of the PGA. That constant level is defined as
the ALC target level, which is set by the ALCREF bits. The level
can be set from 24 dBFS to 1.5 dBFS in 16 steps.
ALC Maximum Gain
The ALCMAX bits (Register 0xC5, Bits[3:0]) set the maximum
gain value that the PGA can reach while under the control of
the ALC. The available gain range is 12 dB to +60 dB in 13 steps.
RMS Average Time
The rms average time is the time taken for the rms value esti-
mation. It is set by the ALCTAV bits (Register 0xC2, Bits[7:4]).
The averaging time range is 1.5 ms to 6.144 sec in 13 steps.
Target Level Ripple Remove
The ALCRIP bits (Register 0xC5, Bits[7:4]) define the ALC
target level ripple range. When the input signal rms level is
within this range, the ALC gain does not change. The ripple
range can be set from 0 dB to 7.5 dB in 16 steps.
For example, if the ALC target level is 6 dB, the ripple is defined as
0.5 dB, and the detected rms value of the input signal is between
6 dB and 6.5 dB, the ALC gain does not change.
Attack (Gain Ramp-Down) Time
Attack time, which is set by the ALCATT bits, is the time that is
required for the PGA gain to ramp down through 90% of its range.
Therefore, the time for the recording level to return to its target
value (limit operation threshold) depends on both the attack
time and the gain adjustment required. If the gain adjustment is
small, the real adjustment time is less than the attack time. The
attack time range is from 1.5 ms to 6.144 sec in 13 steps. In mute
condition, this is the mute attack time.
Decay/Recovery (Gain Ramp-Up) Time
Decay time, which is set by the ALCREC bits, is the time that
is required for the PGA gain to ramp up to 90% of its range.
Therefore, the time required for the recording level to return to
its target value (recovery threshold) depends on both the decay
time and the gain adjustment required. If the gain adjustment is
small, the real adjustment time is less than the decay time. The
recovery time ranges from 6 ms to 24.576 sec in 16 steps.
Recovery Hold Time
Recovery hold time, set by the ALCHLD bits (Register 0xC2,
Bits[3:0]), is the time delay between the detection of the signal
level below the recovery threshold and the PGA gain beginning
to ramp up. The hold time applies only to gain ramp-up; there is
no delay before the gain ramping down when the signal level is
above target. The hold time range is 0 ms to 5.468 sec in 13 steps.
INPUT
SIGNAL
PGA
GAIN
SIGNAL
AFTER
ALC
HOLD
TIME
DECAY
TIME
ATTACK
TIME
ALC
TARGET
LEVEL
0
89
75-
046
Figure 113. Digital PGA and ALC Decay Time, Hold Time, and Attack Time
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