參數(shù)資料
型號(hào)： AD9948KCPZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/28頁(yè)
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROCESSOR 40-LFCSP
標(biāo)準(zhǔn)包裝： 2,500
類型： CCD 信號(hào)處理器，10 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP
包裝： 帶卷 (TR)
REV. 0
–24–
AD9948
3V
ANALOG
SUPPLY
SERIAL
INTERFACE
3
CCD SIGNAL
VD/HD/HBLK INPUTS
CLP/BLK OUTPUT
4
3V
DRIVER
SUPPLY
RG DRIVER
SUPPLY
H DRIVER
SUPPLY
MASTER CLOCK INPUT
3V
ANALOG
SUPPLY
DATA
OUTPUTS
10
H1–H4
4
TOP VIEW
AD9948
PIN 1
IDENTIFIER
30
REFB
29
REFT
28
AVSS
27
CCDIN
26
AVDD
25
CLI
24
TCVDD
23
TCVSS
22
RGVDD
21
RG
NC
1
D1
3
D2
4
DRVDD
6
D3
7
D4
8
D5
9
D6 10
40
NC
39
CLP/PBLK
38
HBLK
37
DVDD
36
DVSS
35
HD
34
VD
33
SCK
32
SDI
31
SL
D7
11
D8
12
(MSB)
D9
13
H1
14
H2
15
HVSS
1
6
HVDD
17
H3
18
H4
19
RGVSS
20
RG OUTPUT
+
DRVSS
5
(LSB) D0
2
4.7 F 0.1 F
0.1 F
4.7 F
0.1 F
4.7 F
0.1 F
1 F
Figure 21. Recommended Circuit Configuration
APPLICATIONS INFORMATION
Circuit Configuration
The AD9948 recommended circuit configuration is shown in
Figure 21. Achieving good image quality from the AD9948
requires careful attention to PCB layout. All signals should be
routed to maintain low noise performance. The CCD output
signal should be directly routed to Pin 27 through a 0.1
F
capacitor. The master clock CLI should be carefully routed to
Pin 25 to minimize interference with the CCDIN, REFT, and
REFB signals.
The digital outputs and clock inputs are located on Pins 2 to 13
and Pins 31 to 39, and should be connected to the digital ASIC
away from the analog and CCD clock signals. Placing series
resistors close to the digital output pins may help to reduce
digital code transition noise. If the digital outputs must drive a
load larger than 20 pF, buffering is recommended to minimize
additional noise. If the digital ASIC can accept gray code, the
AD9948’s outputs can be selected to output data in gray code
format using the control register Bit D5. Gray coding will
help reduce potential digital transition noise compared with
binary coding.
The H1–H4 and RG traces should have low inductance to
avoid excessive distortion of the signals. Heavier traces are
recommended because of the large transient current demand
on H1–H4 from the capacitive load of the CCD. If possible,
physically locating the AD9948 closer to the CCD will reduce
the inductance on these lines. As always, the routing path
should be as direct as possible from the AD9948 to the CCD.
Grounding and Decoupling Recommendations
As shown in Figure 21, a single ground plane is recommended
for the AD9948. This ground plane should be as continuous as
possible, particularly around Pins 23 to 30. This will ensure that
all analog decoupling capacitors provide the lowest possible
impedance path between the power and bypass pins and their
respective ground pins. All high frequency decoupling capacitors
should be located as close as possible to the package pins. It is
recommended that the exposed paddle on the bottom of the
package be soldered to a large pad, with multiple vias connect-
ing the pad to the ground plane.
All the supply pins must be decoupled to ground with good
quality, high frequency chip capacitors. There should also be a
4.7
F or larger bypass capacitor for each main supply—AVDD,
RGVDD, HVDD, and DRVDD—although this is not necessary
for each individual pin. In most applications, it is easier to share
the supply for RGVDD and HVDD, which may be done as long
as the individual supply pins are separately bypassed. A separate
3 V supply may be used for DRVDD, but this supply pin should
still be decoupled to the same ground plane as the rest of the
chip. A separate ground for DRVSS is not recommended.
The reference bypass pins (REFT, REFB) should be decoupled
to ground as close as possible to their respective pins. The analog
input (CCDIN) capacitor should also be located close to the pin.
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