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參數(shù)資料
| 型號： | AD9948KCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/28頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 40-LFCSP |
| 標準包裝： | 2,500 |
| 類型： | CCD 信號處理器，10 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 40-LFCSP |
| 包裝： | 帶卷 (TR) |
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REV. 0
–20–
AD9948
6dB ~ 42dB
CCDIN
DIGITAL
FILTER
CLPOB
DC RESTORE
OPTICAL BLACK
CLAMP
10-BIT
ADC
VGA
DAC
CLAMP LEVEL
REGISTER
8
VGA GAIN
REGISTER
CDS
INTERNAL
VREF
2V FULL SCALE
0dB ~ 18dB
10
PRECISION
TIMING
GENERATION
SHP
SHD
PxGA
1.5V
OUTPUT
DATA
LATCH
REFT
REFB
DOUT
PHASE
V-H
TIMING
GENERATION
SHP SHD
DOUT
PHASE
CLPOB
PBLK
1.0V
2.0V
DOUT
AD9948
PxGA GAIN
REGISTERS
0dB, –2dB, –4dB
1.0 F 1.0 F
1.0 F
Figure 15. Analog Front End Functional Block Diagram
ANALOG FRONT END DESCRIPTION AND OPERATION
The AD9948 signal processing chain is shown in Figure 15. Each
processing step is essential in achieving a high quality image from
the raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal,
adc restore circuit is used with an external 0.1
F series cou-
pling capacitor. This restores the dc level of the CCD signal to
approximately 1.5 V to be compatible with the 3 V supply voltage
of the AD9948.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low frequency noise. The timing
shown in Figure 5 illustrates how the two internally generated
CDS clocks, SHP and SHD, are used to sample the reference
level and the CCD signal level, respectively. The placement of
the SHP and SHD sampling edges is determined by the setting
of the SAMPCONTROL register located at Address 0x63.
Placement of these two clock signals is critical in achieving the
best performance from the CCD.
The gain in the CDS is fixed at 0 dB by default. Using Bits D10
and D11 in the AFE operation register, the gain may be reduced
to –2 dB or –4 dB. This will allow the AD9948 to accept an input
signal of greater than 1 V p-p. See Table VIII for register details.
Table XVI. Adjustable CDS Gain
Operation Register Bits
D11
D10
CDS Gain
Max CDS Input
00
0 dB
1.0 V p-p
01
–2 dB
1.2 V p-p
10
–4 dB
1.6 V p-p
11
0 dB
1.0 V p-p
PxGA
The PxGA provides separate gain adjustment for the individual
color pixels. A programmable gain amplifier with four separate
values, the PxGA has the capability to multiplex its gain value on
a pixel-to-pixel basis (see Figure 16). This allows lower output
color pixels to be gained up to match higher output color pixels.
Also, the PxGA may be used to adjust the colors for white bal-
ance, reducing the amount of digital processing that is needed.
The four different gain values are switched according to the color
steering circuitry. Three different color steering modes for differ-
ent types of CCD color filter arrays are programmable in the AFE
CTLMODE register at Address 0x03 (see Figures 18a to 18c for
timing examples). For example, progressive steering mode accom-
modates the popular Bayer arrangement of red, green, and blue
filters (see Figure 17a).
COLOR
STEERING
CONTROL
4:1
MUX
3
GAIN0
GAIN1
GAIN2
GAIN3
PxGA
PxGA STEERING
MODE
SELECTION
2
8
VD
HD
PxGA GAIN
REGISTERS
CONTROL
REGISTER
BITS D0–D1
SHP/SHD
VGA
CDS
Figure 16. PxGA Block Diagram
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