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參數(shù)資料
| 型號： | AD9937 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with Precision Timing⑩ Generator |
| 中文描述： | CCD信號處理器精確定時⑩發(fā)生器 |
| 文件頁數(shù)： | 5/44頁 |
| 文件大小： | 410K |
| 代理商： | AD9937 |
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AD9937
–5–
REV. 0
TIMING SPECIFICATIONS
(C
L
= 20 pF, AVDD = DVDD = DRVDD = 3 V, f
CLI
= 12 MHz, unless otherwise noted.)
Parameter
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9937 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS
With
Respect
To
Parameter
Min
Max
Unit
AVDD
TCVDD
HVDD
RSVDD
DVDD
DRVDD
RS Output
H1(A
–
D), H2(A, B)Output HVSS
Digital Outputs
Digital Inputs
SCK, SLD, SDA
VRT, VRB
CCDIN
Junction Temperature
Lead Temperature, 10 sec
AVSS
TCVSS
HVSS
RSVSS
DVSS
DRVSS
RSVSS
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
+3.9
+3.9
+3.9
+3.9
+3.9
+3.9
RSVDD + 0.3 V
HVDD + 0.3
DVDD + 0.3
DVDD + 0.3
DVDD + 0.3
AVDD + 0.3
AVDD + 0.3
150
350
V
V
V
V
V
V
V
V
V
V
V
V
°
C
°
C
DVSS
DVSS
DVSS
AVSS
AVSS
ORDERING GUIDE
Temperature
Range
–
25
°
C to +85
°
C
Package
Description
Package
Option
Model
AD9937KCP
Lead Frame
Chip Scale
Package
(LFCSP)
Lead Frame
Chip Scale
Package
(LFCSP)
CP-56
AD9937KCPRL
–
25
°
C to +85
°
C
CP-56
Symbol
Min
Typ
Max
Unit
MASTER CLOCK, VCKM
VCKM Clock Period
VCKM High/Low Pulsewidth
Delay from VCKM Rising Edge to Internal Pixel Position 0
AFE CLAMP PULSES
1
CLPOB Pulsewidth
2
AFE SAMPLE LOCATION
1
(See Figure 13)
SHP Sample Edge to SHD Sample Edge
t
CONV
83.33
ns
ns
ns
41.67
9
t
VCKMDLY
2
20
Pixels
t
S1
33.34
41.67
ns
DATA OUTPUTS
Output Delay from VCLK Rising Edge
Pipeline Delay from SHP/SHD Sampling (See Figure 40)
t
OD
9
9
ns
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
SLD to SCK Setup Time
SCK to SLD Hold Time
SDA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDA Valid Hold
SCK Falling Edge to SDA Valid Read
f
SCLK
t
LS
t
LH
t
DS
t
DH
t
DV
10
10
10
10
10
10
MHz
ns
ns
ns
ns
ns
NOTES
1
Parameter is programmable.
2
Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
Specifications subject to change without notice.
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance
JA
= 24.9
°
C/W
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