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參數(shù)資料
| 型號： | AD9937 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with Precision Timing⑩ Generator |
| 中文描述： | CCD信號處理器精確定時⑩發(fā)生器 |
| 文件頁數(shù)： | 31/44頁 |
| 文件大?。?/td> | 410K |
| 代理商： | AD9937 |
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REV. 0
AD9937
–31–
Controlling LM Pulse Timing
The AD9937 provides an LM output pulse that is fully program-
mable by using the registers in Table XV. Two unique sets of LM
pulses can be preprogrammed using the LMLENx, LMTOG1_x,
and LMTOG2_x (x = 0, 1) registers. Once these pulses are
preprogrammed, they can be individually selected to be output
in any of the five CCD regions by using the LMPATSELn
register (n = 0, 1, 2, 3, 4). The number of repetitions can also be
individually programmed for each CCD region by using the
LMREPn register (n = 0, 1, 2, 3, 4).
The 12-bit H counter and 8-bit LM counters are used for con-
figuring the LM pulse. The 8-bit LM counter resets to 0 when
the 12-bit H counter resets to 0 set by the HDLEN register.
The LMSTART0 and LMSTART1 positions reference the 12-
bit H counter value zero. The 8-bit LM counter begins counting
when LMSTART0 is reached; it counts up to the value set in
the LMLENx register, as shown in Figure 26. The LM pulse
toggle positions reference the 8-bit LM counter.
Figures 26 and 27 provide examples of programming the LM
pulses. Figure 26 shows an example when LMSTART1 is less
than HDLEN. In this case, multiple sets of LM pulses can be
output between the HDLEN lengths. The number of sets is
determined by the value of HDLEN and LMSTART1. Figure 27
shows that only one set of LM pulses will be output when
LMSTART1 is greater than HDLEN.
Table XV. LM Registers
Length
(Bits)
Register
Type
Register Name
Range
Description
LM_INVERT
LMSTART0
*
LMSTART1
*
1
12
12
Control 0x04
Mode_Reg(13)
Mode_Reg(13)
High/Low
0
–
4095 Pixels
0
–
4095 Pixels
LM Inversion Control (1 = Invert Programmed LM)
LM Counter Start Position 1
LM Counter Start Position 2
LMLEN0
LMTOG1_0
LMTOG2_0
LMLEN1
LMTOG1_1
LMTOG2_1
8
8
8
8
8
8
HLM_Reg(8)
HLM_Reg(8)
HLM_Reg(8)
HLM_Reg(9)
HLM_Reg(9)
HLM_Reg(9)
0
–
255 Pixels
0
–
255 Pixels
0
–
255 Pixels
0
–
255 Pixels
0
–
255 Pixels
0
–
255 Pixels
LM Counter Length for LM0
LM0 Toggle Position 1
LM0 Toggle Position 2
LM Counter Length for LM1
LM1 Toggle Position 1
LM1 Toggle Position 2
LMPATSEL0
LMREP0
LMPATSEL1
LMREP1
LMPATSEL2
LMREP2
LMPATSEL3
LMREP3
LMPATSEL4
LMREP4
1
2
1
2
1
2
1
2
1
2
Mode_Reg(15)
Mode_Reg(15)
Mode_Reg(16)
Mode_Reg(16)
Mode_Reg(17)
Mode_Reg(17)
Mode_Reg(18)
Mode_Reg(18)
Mode_Reg(19)
Mode_Reg(19)
High/Low
0
–
3 LM Repetitions
High/Low
0
–
3 LM Repetitions
High/Low
0
–
3 LM Repetitions
High/Low
0
–
3 LM Repetitions
High/Low
0
–
3 LM Repetitions
Selects CCD Region 0 LM Pattern (0 = LM0, 1 = LM1)
LM Repetition Number in CCD Region 0
Selects CCD Region 1 LM Pattern (0 = LM0, 1 = LM1)
LM Repetition Number in CCD Region 1
Selects CCD Region 2 LM Pattern (0 = LM0, 1 = LM1)
LM Repetition Number in CCD Region 2
Selects CCD Region 3 LM Pattern (0 = LM0, 1 = LM1)
LM Repetition Number in CCD Region 3
Selects CCD Region 4 LM Pattern (0 = LM0, 1 = LM1)
LM Repetition Number in CCD Region 4
*
LMSTART0 and LMSTART1 reference the 12-bit HD counter.
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