參數(shù)資料
型號： AD9937
廠商： Analog Devices, Inc.
英文描述： CCD Signal Processor with Precision Timing⑩ Generator
中文描述： CCD信號處理器精確定時⑩發(fā)生器
文件頁數(shù)： 23/44頁
文件大?。?/td> 410K
代理商： AD9937
REV. 0
AD9937
–23–
Table VIII. RS, H1, SHP, SHD, and DOUTPHASE Timing Parameters
Bit Width
(Bits)
Register Name
*
Register Type
Range
Description
RSPOSLOC
RSNEGLOC
H1POSLOC
H1NEGLOC
SHPLOC
SHDLOC
DOUTPHASE
6
6
6
6
6
6
6
Control (Addr 0x06)
Control (Addr 0x06)
Control (Addr 0x06)
Control (Addr 0x06)
Control (Addr 0x05)
Control (Addr 0x05)
Control (Addr 0x05)
0
–
47 Edge Location
0
–
47 Edge Location
0
–
47 Edge Location
0
–
47 Edge Location
0
–
47 Edge Location
0
–
47 Edge Location
0
–
47 Edge Location
Falling Edge Location for RS
Falling Edge Location for RS
Positive Edge Location for H1
Negative Edge Location for H1
Sample Location for SHP
Sample Location for SHD
Phase Location of Data Output [9:0]
*
The 2 MSB bits are used to select the quadrant.
Table IX. Precision Timing Edge Locations for RS, H1, SHP, SHD, and DOUTPHASE
Quadrant
(Range)
RS Rising Edge
RSPOSLOC
RS Falling Edge
RSNEGLOC
Signal Name
RS
I
II
III
IV
P[0] to P[11]
P[12] to P[23]
P[24] to P[35]
P[36] to P[47]
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
Quadrant
(Range)
H1 Rising Edge
H1POSLOC
H1 Falling Edge
H1NEGLOC
Signal Name
H1
I
II
III
IV
P[0] to P[11]
P[12] to P[23]
P[24] to P[35]
P[36] to P[47]
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
Quadrant
(Range)
CDS (SHP) Rising Edge
SHPLOC
CDS (SHD) Falling Edge
SHDLOC
Signal Name
CDS (Internal)
I
II
III
IV
P[0] to P[11]
P[12] to P[23]
P[24] to P[35]
P[36] to P[47]
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
Quadrant
(Range)
DOUT Rising Edge
DOUTPHASE
DOUT Falling Edge
(Not Programmable)
Signal Name
Data Output[9:0]
I
II
III
IV
P[0] to P[11]
P[12] to P[23]
P[24] to P[35]
P[36] to P[47]
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
DOUTPHASE + 24 Steps
DOUTPHASE + 24 Steps
DOUTPHASE + 24 Steps
DOUTPHASE + 24 Steps
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