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參數(shù)資料
| 型號(hào)： | AD9937 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with Precision Timing⑩ Generator |
| 中文描述： | CCD信號(hào)處理器精確定時(shí)⑩發(fā)生器 |
| 文件頁(yè)數(shù)： | 41/44頁(yè) |
| 文件大?。?/td> | 410K |
| 代理商： | AD9937 |
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REV. 0
AD9937
–41–
VDD
(INPUT)
VD
(OUTPUT)
DIGITAL
OUTPUTS
VCKM
HD
(OUTPUT)
OUTCONT
(INTERNAL)
ODD FIELD
EVEN FIELD
ODD FIELD
AFE_STBY
(REGISTER)
DIG_STBY
(REGISTER)
3
VCLK
SERIAL
WRITES
4
RS, H2(A, B), LM
V1A/B, V2, V3A/B, V4, TG1A, TG1B, TG3A, TG3B,
OFD, H1(A, B, C, D)
Figure 39. Recommended Power-Down Sequence
N
N + 1
N + 2
N + 4
N + 5
N – 10
N – 9
N – 8
N – 6
NOTES
1. RECOMMENDED PLACEMENT FOR VCKM RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.
2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
3. OUTPUT DATA LATENCY IS NINE VCKM CYCLES.
SHP
SHD
VCKM
OUTPUT
DATA
CCD
SIGNAL
N + 7
N + 8
N + 10
N – 4
N – 3
N – 2
N – 1
N
N + 3
N + 6
N + 9
N – 7
N – 5
CYCLE 1
CYCLE 2
CYCLE 3
CYCLE 4
CYCLE 5
CYCLE 6
CYCLE 7
CYCLE 8
CYCLE 9
t
S1
t
ID
t
ID
t
S2
N + 11
t
CP
t
OD
Figure 40. Pipeline Latency
POWER-DOWN SEQUENCE
The following sequence is recommended when AD9937 is being
powered down. (Refer to Figure 39 for each step.)
1. Write a 0 to the OUTCONT_REG register (addr 0x01).
2. Write a 0 to the DIG_STBY and AFE_STBY registers
(addr 0x02). This will put the digital and analog circuits into
the standby operating mode.
3. Stop VCKM clock.
4. Turn off power supplies to AD9937.
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