參數(shù)資料
型號(hào)： AD9898
廠商： Analog Devices, Inc.
英文描述： CCD Signal Processor with Precision Timing⑩ Generator
中文描述： CCD信號(hào)處理器精確定時(shí)⑩發(fā)生器
文件頁(yè)數(shù)： 45/52頁(yè)
文件大小： 557K
代理商： AD9898
REV. 0
AD9898
–45–
VARIABLE GAIN AMPLIFIER
The VGA provides a gain range of 6 dB to 40 dB, programmable
with 10-bit resolution through the serial digital interface. The
minimum gain of 6 dB is needed to match a 1 V input signal
with the ADC full-scale range of 2 V.
The VGA gain curve follows a linear-in-dB characteristic. The
exact VGA gain can be calculated for any gain register value
using the equation
(
0 035
.
where the code range is 0 to 1023. Figure 50 shows a typical
AD9898 VGA gain curve.
Gain
Code
=
×
)
+
5 3
.
VGA GAIN REGISTER CODE
60
127
V
12
255
383
511
639
767
895
1023
18
24
30
36
42
Figure 50. VGA Gain Curve
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain and to track low frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with a fixed
black level reference, selected by the user in the clamp level
register. Any value between 0 LSB and 63 LSB may be pro-
grammed with 6-bit resolution. The resulting error signal is
filtered to reduce noise, and the correction value is applied to
the ADC input through a D/A converter. Normally the optical
black clamp loop is turned on once per horizontal line, but this
loop can be updated more slowly to suit a particular application.
The optical black clamp is controlled by the CLPOB signal,
which is fully programmable (see Horizontal Clamping and
Blanking section). System timing examples are shown in the
Horizontal Timing Sequence Example section. The CLPOB
pulse should be placed during the CCD’s optical black pixel.
It is recommended that the CLPOB pulse duration be at least
20 pixels wide. Shorter pulsewidths may be used, but the ability
to track low frequency variations in the black level will be reduced.
A/D Converter
The AD9898 uses a high performance 10-bit ADC architecture,
optimized for high speed and low power. Differential nonlinearity
(DNL) performance is typically better than 0.5 LSB. The ADC
uses a 2 V input range. Better noise performance results from
using a larger ADC full-scale range.
Digital I/O States for Different Operating Conditions
Table XXVI describes the state of the digital I/Os for different
operating conditions.
Table XXVI. I/O Levels
I/O
OCONT_REG
1
= 0
SW_RESET
DIGSTBY
SYNC
DCLK1
DCLK2
VD
2
HD
2
RG
H1
H2
V1
V2
V3
V4
SUBCK
VSG1
VSG2
STROBE
MSHUT
FD
ACTIVE
ACTIVE
H
H
L
H
L
H
H
H
H
H
H
H
L
L
H
ACTIVE
ACTIVE
H
H
L
H
L
L
L
L
H
H
L
H
L
L
L
L
L
H
H
L
H
L
H
L
L
H
H
H
H
L
L
L
ACTIVE
ACTIVE
H
H
ACTIVE
ACTIVE
ACTIVE
FREEZE
FREEZE
FREEZE
FREEZE
FREEZE
FREEZE
FREEZE
FREEZE
FREEZE
FREEZE
NOTES
1
OUTCONT_REG is a register setting located at Addr 0x05. It defaults to 0 at power-up.
2
VD and HD operating in master mode.
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