參數(shù)資料
型號： AD9898
廠商： Analog Devices, Inc.
英文描述： CCD Signal Processor with Precision Timing⑩ Generator
中文描述： CCD信號處理器精確定時⑩發(fā)生器
文件頁數(shù)： 21/52頁
文件大?。?/td> 557K
代理商： AD9898
REV. 0
AD9898
–21–
Table IX. Precision Timing Edge Locations for RG, H1, SHP, SHD, DCLK, and DOUTPHASE
RG Rising Edge
(Not Programmable)
RG Falling Edge
Signal Name
Quadrant
RGNEGLOC
Quadrant Range
RG
I
II
III
IV
Fixed at 000000
Fixed at 000000
Fixed at 000000
Fixed at 000000
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
P[0] to P[11]
P[12] to P[23]
P[24] to P[35]
P[36] to P[47]
H1 Rising Edge
H1 Falling Edge
Signal Name
Quadrant
H1POSLOC
Quadrant Range
(Not Programmable)
H1
I
II
III
IV
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
P[0] to P[11]
P[12] to P[23]
P[24] to P[35]
P[36] to P[47]
H1POSLOC + 24 Steps
H1POSLOC + 24 Steps
H1POSLOC + 24 Steps
H1POSLOC + 24 Steps
cds Rising Edge
cds Falling Edge
Signal Name
Quadrant
SHPLOC
Quadrant Range
SHDLOC
Quadrant Range
cds
I
II
III
IV
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
P[0] to P[11]
P[12] to P[23]
P[24] to P[35]
P[36] to P[47]
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
P[0] to P[11]
P[12] to P[23]
P[24] to P[35]
P[36] to P[47]
Data Output[9:0] Rising Edge
DOUTPHASE
Data Output[9:0] Falling Edge
(Not Programmable)
Signal Name
Quadrant
Quadrant Range
Data Output[9:0]
I
II
III
IV
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
P[0] to P[11]
P[12] to P[23]
P[24] to P[35]
P[36] to P[47]
DOUTPHASE + 24 Steps
DOUTPHASE + 24 Steps
DOUTPHASE + 24 Steps
DOUTPHASE + 24 Steps
Signal Name
DCLKPHASE Value
DCLKPHASE Rising Edge
DCLKPHASE Falling Edge
DCLK1
00
01
10
11
P[6]
P[16]
P[26]
P[36]
P[26]
P[36]
P[06]
P[16]
Table VIII. RG, H1, SHP, SHD, DCLK, and DOUTPHASE Timing Parameters
Register Name
Bit Width
Register Type
Range
Description
RGNEGLOC
H1POSLOC
SHPLOC
SHDLOC
DOUTPHASE
DCLKPHASE
6
6
6
6
6
6
Control (Addr 0x03)
Control (Addr 0x03)
Control (Addr 0x02)
Control (Addr 0x02)
Control (Addr 0x02)
Control (Addr 0x02)
0–47 Edge Location
0–47 Edge Location
0–47 Edge Location
0–47 Edge Location
0–47 Edge Location
0–47 Edge Location
Falling Edge Location for RG
Positive Edge Location for H1
Sample Location for SHP
Sample Location for SHD
Phase Location of Data Output [9:0]
Positive Edge of DCLK 1
The 2 MSB are used to select the quadrant.
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