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參數資料
| 型號： | AD9898 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with Precision Timing⑩ Generator |
| 中文描述： | CCD信號處理器精確定時⑩發(fā)生器 |
| 文件頁數： | 24/52頁 |
| 文件大?。?/td> | 557K |
| 代理商： | AD9898 |
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REV. 0
–24–
AD9898
HORIZONTAL AND VERTICAL SYNCHRONOUS TIMING
The HD and VD output pulses are programmable using the
registers listed in Table XI. The HD output is asserted low at
the start of the horizontal line shift. The VD output is asserted
low at the start of each line. As shown in Figure 18, the 11-bit
VD counter is used to count the number of lines set by the
VDLEN register. The 12-bit HD counter is used to count the
number of pixels in each line set by the HDLEN register. For
example, if the CCD array size is 2000 lines by 2100 pixels per
line, VDLEN = 2000 and HDLEN = 0xC28. The HLEN regis-
ter sets the HL counter that is used as a reference for the rising
edge of the HD pulse.
Table XI. HD and VD Registers
Register
Name
Bit
Width
Reference
Counter
Register Type
Range
Description
HDLEN
HLEN
HDRISE
HDLASTLEN
*
VDLEN
VDRISE
12
10
10
12
11
4
Sys_Reg(12)
Sys_Reg(12)
Sys_Reg(16)
Mode_Reg(1)
Mode_Reg(1)
Sys_Reg(16)
0–4095 Pixels
0–1023 Pixels
0–1023 Pixels
0–4095 Pixels
0–2047 Lines
0–15 Lines
12-Bit Gray Code Counter Value
10-Bit HL Counter Value
HD Rise Position
HD Last Line Length
VD Counter Value
VD Rise Position
HL
HD
VD
*
Register value must be a gray code number. (See Gray Code Registers section.)
001
000
002
N 2048
HDLASTLEN
SETUP
HDLEN
HLEN
11-BIT
VD COUNTER
12-BIT
GRAY COUNTER
+ SETUP
10-BIT
HL COUNTER
VD
HD
LINE LENGTH =
HDLEN + 4
1. THE SETUP DELAY IS 4 CLI CYCLES. THE ACTUAL LENGTH OF ONE LINE IS 4
MORE CYCLES THAN THE VALUE SET IN HDLEN AND HDLASTLEN DUE TO SETUP DELAY.
2. VDRISE REFERENCES THE 11-BIT VD COUNTER.
3. HDRISE REFERENCES THE 10-BIT HL COUNTER.
PROGRAMMABLE CLOCK POSITIONS
1. HDRISE (SYS_REG(16))
2. VDRISE (SYS_REG(16))
VDLEN
2
1
Figure 18. VD and HD Horizontal Timing
Special Note about the HDLEN Register
The 12-bit HD counter value must be programmed using a gray
code number. There is also a 4-clock cycle setup period that
must be considered when determining the HDLEN register
value, as shown in Figure 18. As a result of the 4-clock cycle
setup period, the value of HDLEN is always equal to the actual
number of pixels per line minus four. For example, if there are
2100 pixels per line, HDLEN equals (2100 – 4) = 2096. The
gray code value of 2096 is 0xC28, which is what would be pro-
grammed in the HDLEN register.
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