參數(shù)資料
型號(hào)： AD9898
廠商： Analog Devices, Inc.
英文描述： CCD Signal Processor with Precision Timing⑩ Generator
中文描述： CCD信號(hào)處理器精確定時(shí)⑩發(fā)生器
文件頁(yè)數(shù)： 13/52頁(yè)
文件大?。?/td> 557K
代理商： AD9898
REV. 0
AD9898
–13–
Table II. System Register Address Map (Addr 0x14) (continued)
Bit
Width
Default
(Decimal) Register Name
Register
Content
Register Description
Sys_Reg(9)
(31:23)
22
21
20
19
(18:10)
(9:1)
0
9
1
1
1
1
9
9
1
89
0
0
1
1
0
60
VTPLEN3
V1STARTPOL3
V2STARTPOL3
V3STARTPOL3
V4STARTPOL3
V1TOG1POS3
V1TOG2POS3
V2TOG1POS3 [8]
Vertical Sequence No. 3: Length between Repetitions
Vertical Sequence No. 3: V1 Start Polarity
Vertical Sequence No. 3: V2 Start Polarity
Vertical Sequence No. 3: V3 Start Polarity
Vertical Sequence No. 3: V4 Start Polarity
Vertical Sequence No. 3: V1 Toggle Position 1
Vertical Sequence No. 3: V1 Toggle Position 2
Sys_Reg(10)
(31:24)
(23:15)
(14:6)
(5:0)
8
9
9
6
30
90
0
V2TOG1POS3 [7:0]
V2TOG2POS3
V3TOG1POS3
V3TOG2POS3 [8:3]
Vertical Sequence No. 3: V2 Toggle Position 1
Vertical Sequence No. 3: V2 Toggle Position 2
Vertical Sequence No. 3: V3 Toggle Position 1
Sys_Reg(11)
(31:29)
(28:20)
(19:11)
(10:1)
0
3
9
9
10
1
60
30
90
0
V3TOG2POS3 [2:0]
V4TOG1POS3
V4TOG2POS3
HBLKHPOS
Vertical Sequence No. 3: V3 Toggle Position 2
Vertical Sequence No. 3: V4 Toggle Position 1
Vertical Sequence No. 3: V4 Toggle Position 2
H1 Pulse ON Position during Blanking Period
Unused
Sys_Reg(12)
(31:20)
(19:10)
(9:1)
0
12
10
9
1
2283
130
100
HDLEN
*
HLEN
OLEN
BLLEN [8]
12-Bit Gray Code HD Counter Value (Gray Code Number)
10-Bit HL Counter Value
9-Bit OL Counter Value
Sys_Reg(13)
(31:24)
(23:16)
(15:5)
(4:0)
8
8
11
5
0
118
1048
BLLEN[7:0]
MSHUTLEN
VSGTOG1_0
VSGTOG1_1 [10:6]
9-Bit BL Counter Value
MSHUT Sequence Length
VSG Sequence No. 1 Toggle Position 1
Sys_Reg(14)
(31:26)
(25:18)
(17:9)
(8:0)
6
8
9
9
1198
60
19
88
VSGTOG1_1 [5:0]
VSGLEN
SUBCK1TOG1
SUBCK1TOG2
VSG Sequence No. 2 Toggle Position 1
VSG Pulsewidth
SUBCK1 First Toggle Position
SUBCK1 Second Toggle Position
Sys_Reg(15)
(31:23)
(22:14:)
(13:2)
(1:0)
9
9
12
2
19
88
2243
SUBCK2TOG1
SUBCK2TOG2
CLPTOG1
*
CLPTOG2 [11]
*
SUBCK2 First Toggle Position
SUBCK2 Second Toggle Position
CLPOB Toggle Position No. 1
Sys_Reg(16)
(31:22)
(21:18)
(17:8)
(7:0)
10
4
10
8
2278
9
120
CLPTOG2 [10:0]
*
VDRISE
HDRISE
CLPOB Toggle Position No. 2
VD Toggle Position No. 1
HD Toggle Position No. 2
Unused
*
Register value must be a gray code number. (See Gray Code Registers section.)
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