參數(shù)資料
型號： AD9898
廠商： Analog Devices, Inc.
英文描述： CCD Signal Processor with Precision Timing⑩ Generator
中文描述： CCD信號處理器精確定時⑩發(fā)生器
文件頁數(shù)： 12/52頁
文件大?。?/td> 557K
代理商： AD9898
REV. 0
–12–
AD9898
Table II. System Register Address Map (Addr 0x14)
Bit
Width
Default
(Decimal) Register Name
Register
Content
Register Description
Sys_Reg(0)
(31:24)
(23:0)
8
24
NA
NA
System_Reg_Addr
System_Number_N
System Register Address Is (Addr 0x14)
Number N Register Writes (0x000000 = Write All Registers)
Sys_Reg(1)
(31:23)
22
21
20
19
(18:10)
(9:1)
0
9
1
1
1
1
9
9
1
37
0
0
1
1
0
19
0
VTPLEN0
V1STARTPOL0
V2STARTPOL0
V3STARTPOL0
V4STARTPOL0
V1TOG1POS0
V1TOG2POS0
V2TOG1POS0 [8]
Vertical Sequence No. 0: Length between Repetitions
Vertical Sequence No. 0: V1 Start Polarity
Vertical Sequence No. 0: V2 Start Polarity
Vertical Sequence No. 0: V3 Start Polarity
Vertical Sequence No. 0: V4 Start Polarity
Vertical Sequence No. 0: V1 Toggle Position 1
Vertical Sequence No. 0: V1 Toggle Position 2
Sys_Reg(2)
(31:24)
(23:15)
(14:6)
(5:0)
8
9
9
6
12
31
0
V2TOG1POS0 [7:0]
V2TOG2POS0
V3TOG1POS0
V3TOG2POS0 [8:3]
Vertical Sequence No. 0: V2 Toggle Position 1
Vertical Sequence No. 0: V2 Toggle Position 2
Vertical Sequence No. 0: V3 Toggle Position 1
Sys_Reg(3)
(31:29)
(28:20)
(19:11)
(10:2)
1
0
3
9
9
9
1
1
19
12
31
104
0
0
V3TOG2POS0 [2:0]
V4TOG1POS0
V4TOG2POS0
VTPLEN1
V1STARTPOL1
V2STARTPOL1
Vertical Sequence No. 0: V3 Toggle Position 2
Vertical Sequence No. 0: V4 Toggle Position 1
Vertical Sequence No. 0: V4 Toggle Position 2
Vertical Sequence No. 1: Length between Repetitions
Vertical Sequence No. 1: V1 Start Polarity
Vertical Sequence No. 1: V2 Start Polarity
Sys_Reg(4)
31
30
(29:21)
(20:12)
(11:3)
(2:0)
1
1
9
9
9
3
1
1
18
58
47
V3STARTPOL1
V4STARTPOL1
V1TOG1POS1
V1TOG2POS1
V2TOG1POS1
V2TOG2POS1 [8:6]
Vertical Sequence No. 1: V3 Start Polarity
Vertical Sequence No. 1: V4 Start Polarity
Vertical Sequence No. 1: V1 Toggle Position 1
Vertical Sequence No. 1: V1 Toggle Position 2
Vertical Sequence No. 1: V2 Toggle Position 1
Sys_Reg(5)
(31:26)
(25:17)
(16:8)
(7:0)
6
9
9
8
96
0
76
V2TOG2POS1 [5:0]
V3TOG1POS1
V3TOG2POS1
V4TOG1POS1 [8:1]
Vertical Sequence No. 1: V2 Toggle Position 2
Vertical Sequence No. 1: V3 Toggle Position 1
Vertical Sequence No. 1: V3 Toggle Position 2
Sys_Reg(6)
31
(30:22)
(21:13)
12
11
10
9
(8:0)
1
9
9
1
1
1
1
9
38
105
57
0
0
1
1
0
V4TOG1POS1 [0]
V4TOG2POS1
VTPLEN2
V1STARTPOL2
V2STARTPOL2
V3STARTPOL2
V4STARTPOL2
V1TOG1POS2
Vertical Sequence No. 1: V4 Toggle Position 1
Vertical Sequence No. 1: V4 Toggle Position 2
Vertical Sequence No. 2: Length between Repetitions
Vertical Sequence No. 2: V1 Start Polarity
Vertical Sequence No. 2: V2 Start Polarity
Vertical Sequence No. 2: V3 Start Polarity
Vertical Sequence No. 2: V4 Start Polarity
Vertical Sequence No. 2: V1 Toggle Position 1
Sys_Reg(7)
(31:23)
(22:14)
(13:5)
(4:0)
9
9
9
5
29
19
48
V1TOG2POS2
V2TOG1POS2
V2TOG2POS2
V3TOG1POS2 [8:4]
Vertical Sequence No. 2: V1 Toggle Position 2
Vertical Sequence No. 2: V2 Toggle Position 1
Vertical Sequence No. 2: V2 Toggle Position 2
Sys_Reg(8)
(31:28)
(27:19)
(18:10)
(9:1)
0
4
9
9
9
1
0
29
19
48
V3TOG1POS2 [3:0]
V3TOG2POS2
V4TOG1POS2
V4TOG2POS2
Vertical Sequence No. 2: V3 Toggle Position 1
Vertical Sequence No. 2: V3 Toggle Position 2
Vertical Sequence No. 2: V4 Toggle Position 1
Vertical Sequence No. 2: V4 Toggle Position 2
Unused
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