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參數(shù)資料
| 型號： | AD9887AKSZ-100 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 應(yīng)用： | 圖形卡，VGA 接口 |
| 接口： | 模擬和數(shù)字 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-MQFP（28x28） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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REV. 0
AD9887
–37–
Write to four consecutive control registers
Start signal
Slave Address byte (R/W bit = LOW)
Base Address byte
Data byte to base address
Data byte to (base address + 1)
Data byte to (base address + 2)
Data byte to (base address + 3)
Stop signal
Read from one control register
Start signal
Slave Address byte (R/W bit = LOW)
Base Address byte
Start signal
Slave Address byte (R/W bit = HIGH)
Data byte from base address
Stop signal
Read from four consecutive control registers
Start signal
Slave Address byte (R/W bit = LOW)
Base Address byte
Start signal
Slave Address byte (R/W bit = HIGH)
Data byte from base address
Data byte from (base address + 1)
Data byte from (base address + 2)
Data byte from (base address + 3)
Stop signal
BIT 7
SDA
SCL
ACK
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Figure 37. Serial Interface—Typical Byte Transfer
Table LIV. Control of the Sync Block Muxes via the
Serial Register
Control
Mux
Serial Bus
Bit
Nos.
Control Bit
State
Result
1 and 2
12H: Bit 4
0
Pass Hsync
1
Pass Sync-on-Green
3
12H: Bit 1
0
Pass Coast
1
Pass Vsync
4
12H: Bit 2
0
Pass Vsync
1
Pass Sync Separator Signal
5, 6, and 7 11H: Bit 3
0
Pass Digital Interface Signals
1
Pass Analog Interface Signals
THEORY OF OPERATION (SYNC PROCESSING)
This section is devoted to the basic operation of the sync process-
ing engine (refer to Figure 37 Sync Processing Block Diagram).
Sync Slicer
The purpose of the sync slicer is to extract the sync signal from
the green graphics channel. A sync signal is not present on all
graphics systems, only those with “sync-on-green.” The sync
signal is extracted from the green channel in a two step process.
First, the SOG input is clamped to its negative peak (typically
0.3 V below the black level). Next, the signal goes to a compara-
tor with a trigger level that is 0.15 V above the clamped level.
The “sliced” sync is typically a composite sync signal containing
both Hsync and Vsync.
Sync Separator
A sync separator extracts the Vsync signal from a composite
sync signal. It does this through a low-pass lter-like or integrator-
like operation. It works on the idea that the Vsync signal stays
active for a much longer time than the Hsync signal, so it rejects
any signal shorter than a threshold value, which is somewhere
between an Hsync pulsewidth and a Vsync pulsewidth.
The sync separator on the AD9887 is simply an 8-bit digital
counter with a 5 MHz clock. It works independently of the
polarity of the composite sync signal. (Polarities are determined
elsewhere on the chip.) The basic idea is that the counter counts
up when Hsync pulses are present. But since Hsync pulses are
relatively short in width, the counter only reaches a value of N
before the pulse ends. It then starts counting down eventually
reaching 0 before the next Hsync pulse arrives. The specic
value of N will vary for different video modes, but will always be
less than 255. For example with a 1
s width Hsync, the counter
will only reach 5 (1
s/200 ns = 5). Now, when Vsync is present
on the composite sync the counter will also count up. However,
since the Vsync signal is much longer, it will count to a higher
number M. For most video modes, M will be at least 255. So,
Vsync can be detected on the composite sync signal by detecting
when the counter counts to higher than N. The specic count
that triggers detection (T) can be programmed through the
serial register (0fh).
Once Vsync has been detected, there is a similar process to detect
when it goes inactive. At detection, the counter rst resets to 0,
then starts counting up when Vsync goes away. Similar to the
previous case, it will detect the absence of Vsync when the
counter reaches the threshold count (T). In this way, it will
reject noise and/or serration pulses. Once Vsync is detected to
be absent, the counter resets to 0 and begins the cycle again.
SDA
SCL
tBUFF
tSTAH
tDHO
tDSU
tDAL
tDAH
tSTASU
tSTOSU
Figure 36. Serial Port Read/
Write Timing
OBSOLETE
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9887AKSZ-1001 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887AKSZ-140 | 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9887AKSZ-1401 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887AKSZ-170 | 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9887AKSZ-170 | 制造商:Analog Devices 功能描述:IC DUAL DISPLAY INTERFACE |
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