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參數(shù)資料
| 型號： | AD9887AKSZ-100 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 標準包裝： | 24 |
| 應(yīng)用： | 圖形卡，VGA 接口 |
| 接口： | 模擬和數(shù)字 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-MQFP（28x28） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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REV. 0
AD9887
–35–
DIGITAL CONTROL
13
7:0
Sync Separator Threshold
This register is used to set the responsiveness of the sync
separator. It sets how many pixel clock pulses the sync
separator must count to before toggling high or low. It
works like a low-pass lter to ignore Hsync pulses in order
to extract the Vsync signal. This register should be set to
some number greater than the maximum Hsync pulsewidth.
The default for this register is 32.
CONTROL BITS
14
2
Scan Enable
This register is used to enable the scan function. When
enabled, data can be loaded into the AD9887 outputs
serially with the scan function. The scan function utilizes
three pins (SCANIN, SCANOUT, and SCANCLK). These
pins are described in Table I.
Table XLV. Scan Enable Settings
Scan Enable
Result
0
Scan Function Disabled
1
Scan Function Enabled
The default for scan enable is 0 (disabled).
14
1
Coast Input Polarity Override
This register is used to override the internal circuitry that
determines the polarity of the coast signal going into
the PLL.
Table XLVI. Coast Input Polarity Override Settings
Override Bit
Result
0
Coast Polarity Determined by Chip
1
Coast Polarity Determined by User
The default for coast polarity override is 0 (polarity
determined by chip).
14
0
HSYNC Input Polarity Override
This register is used to override the internal circuitry that
determines the polarity of the Hsync signal going into
the PLL.
Table XLVII. HSYNC Input Polarity Override Settings
Override Bit
Result
0
Hsync Polarity Determined by Chip
1
Hsync Polarity Determined by User
The default for Hsync polarity override is 0 (polarity
determined by chip).
15
7
HSYNC Input Polarity Status
This bit reports the status of the Hsync input polarity
detection circuit. It can be used to determine the polarity
of the Hsync input. The detection circuit’s location is
shown in the Sync Processing Block Diagram (Figure 38).
Table XLVIII. Detected HSYNC Input Polarity Status
Hsync Polarity
Status
Result
0
Hsync Polarity is Negative.
1
Hsync Polarity is Positive.
15
6
VSYNC Output Polarity Status
This bit reports the status of the Vsync output polarity
detection circuit. It can be used to determine the polarity
of the Vsync input. The detection circuit’s location is
shown in the Sync Processing Block Diagram (Figure 38).
Table XLIX. Detected VSYNC Input Polarity Status
Vsync Polarity
Status
Result
0
Vsync Polarity is Active Low.
1
Vsync Polarity is Active High.
15
5
Coast Input Polarity Status
This bit reports the status of the coast input polarity
detection circuit. It can be used to determine the polar-
ity of the coast input. The detection circuit’s location is
shown in the Sync Processing Block Diagram (Figure 38).
Table L. Detected Coast Input Polarity Status
Coast Polarity
Status
Result
0
Coast Polarity is Negative.
1
Coast Polarity is Positive.
16
7–3
Sync-on-Green Slicer Threshold
This register allows the comparator threshold of the
Sync-on-Green slicer to be adjusted. This register adjusts
the comparator threshold in steps of 10 mV. A setting of zero
results in a 330 mV threshold. The setting of 31 results in
a 10 mV threshold.
The default setting is 23 and corresponds to a threshold
value of 70 mV.
17
7–0
Pre-Coast
This register allows the Coast signal to be applied prior
to the Vsync signal. This is necessary in cases where pre-
equalization pulses are present. The step size for this
control is one Hsync period.
The default is 0.
18
7–0
Post-Coast
This register allows the coast signal to be applied follow-
ing to the Vsync signal. This is necessary in cases where
post-equalization pulses are present. The step size for this
control is one Hsync period.
The default is 0.
19
7–0
Test Register
Must be set to default.
1A
7–0
Test Register
Must be set to 41H for proper operation.
OBSOLETE
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9887AKSZ-1001 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887AKSZ-140 | 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9887AKSZ-1401 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887AKSZ-170 | 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9887AKSZ-170 | 制造商:Analog Devices 功能描述:IC DUAL DISPLAY INTERFACE |
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