- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1894 > AD9887AKSZ-100 (Analog Devices Inc)IC INTRFACE ANALOG/DVI 160-MQFP PDF資料下載
參數(shù)資料
| 型號： | AD9887AKSZ-100 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 標準包裝： | 24 |
| 應(yīng)用： | 圖形卡，VGA 接口 |
| 接口： | 模擬和數(shù)字 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-MQFP（28x28） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
REV. 0
AD9887
–29–
2-WIRE SERIAL CONTROL REGISTER DETAIL
CHIP IDENTIFICATION
00
7–0
Chip Revision
Bits 7 through 4 represent functional revisions to the
analog interface. Changes in these bits will generally
indicate that software and/or hardware changes will be
required for the chip to work properly. Bits 3 through 0
represent nonfunctional related revisions and are reset to
0000 whenever the MSBs are changed. Changes in these
bits are considered transparent to the user.
PLL DIVIDER CONTROL
01
7–0
PLL Divide Ratio MSBs
The eight most signicant bits of the 12-bit PLL divide ratio
PLLDIV. (The operational divide ratio is PLLDIV + 1.)
The PLL derives a pixel clock from the incoming Hsync
signal. The pixel clock frequency is then divided by an
integer value, such that the output is phase-locked to
Hsync. This PLLDIV value determines the number of
pixel times (pixels plus horizontal blanking overhead) per
line. This is typically 20% to 30% more than the number
of active pixels in the display.
The 12-bit value of the PLL divider supports divide ratios
from 221 to 4095. The higher the value loaded in this
register, the higher the resulting clock frequency with
respect to a xed Hsync frequency.
VESA has established some standard timing specications,
which will assist in determining the value for PLLDIV as
a function of horizontal and vertical display resolution
and frame rate (Table VII).
However, many computer systems do not conform pre-
cisely to the recommendations, and these numbers should
be used only as a guide. The display system manufacturer
should provide automatic or manual means for optimizing
PLLDIV. An incorrectly set PLLDIV will usually produce
one or more vertical noise bars on the display. The greater
the error, the greater the number of bars produced.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 69h, PLLDIVL = Dxh).
The AD9887 updates the full divide ratio only when the
LSBs are changed. Writing to this register by itself will not
trigger an update.
02
7–4
PLL Divide Ratio LSBs
The four least signicant bits of the 12-bit PLL divide ratio
PLLDIV. The operational divide ratio is PLLDIV + 1.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 69h, PLLDIVL = Dxh).
The AD9887 updates the full divide ratio only when this
register is written.
CLOCK GENERATOR CONTROL
03
7 TEST
Set to One
03
6–5
VCO Range Select
Two bits that establish the operating range of the clock
generator.
VCORNGE must be set to correspond with the desired
operating frequency (incoming pixel rate).
The PLL gives the best jitter performance at high fre-
quencies. For this reason, in order to output low pixel
rates and still get good jitter performance, the PLL actu-
ally operates at a higher frequency but then divides down
the clock rate afterwards. Table X shows the pixel rates
for each VCO range setting. The PLL output divisor is
automatically selected with the VCO range setting.
Table X. VCO Ranges
VCORNGE
Pixel Rate Range
00
12–35
01
35–70
10
70–110
11
110–140
The power-up default value is = 01.
03
4–2
CURRENT Charge Pump Current
Three bits that establish the current driving the loop lter
in the clock generator.
Table XI. Charge Pump Currents
CURRENT
Current ( A)
000
50
001
100
010
150
011
250
100
350
101
500
110
750
111
1500
See Table VII for the recommended CURRENT settings.
The power-up default value is CURRENT = 001.
04
7–3
Clock Phase Adjust
A ve-bit value that adjusts the sampling phase in 32 steps
across one pixel time. Each step represents an 11.25
° shift
in sampling phase.
The power-up default value is 16.
CLAMP TIMING
05
7–0
Clamp Placement
An eight-bit register that sets the position of the internally
generated clamp.
When EXTCLMP = 0, a clamp signal is generated inter-
nally, at a position established by the clamp placement and
for a duration set by the clamp duration. Clamping is
started (Clamp Placement) pixel periods after the trailing
edge of Hsync. The clamp placement may be programmed
to any value between 1 and 255. A value of 0 is not
supported.
The clamp should be placed during a time that the input
signal presents a stable black-level reference, usually the
back porch period between Hsync and the image.
When EXTCLMP = 1, this register is ignored.
OBSOLETE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9887AKSZ-140 | IC INTRFACE ANALOG/DVI 160-MQFP |
| AD9888KSZ-170 | IC ANALOG INTRFC 170MSPS 128MQFP |
| AD9895KBCZRL | IC CCD SIGNAL PROC/GEN 64-CSPBGA |
| AD9910BSVZ-REEL | IC DDS 1GSPS 14BIT PAR 100TQFP |
| AD9911BCPZ-REEL7 | IC DDS 500MSPS DAC 10BIT 56LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9887AKSZ-1001 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887AKSZ-140 | 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9887AKSZ-1401 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887AKSZ-170 | 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9887AKSZ-170 | 制造商:Analog Devices 功能描述:IC DUAL DISPLAY INTERFACE |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。