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參數(shù)資料
| 型號： | AD9887AKSZ-100 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 標準包裝： | 24 |
| 應(yīng)用： | 圖形卡，VGA 接口 |
| 接口： | 模擬和數(shù)字 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-MQFP（28x28） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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REV. 0
AD9887
–23–
DIGITAL INTERFACE PIN DESCRIPTIONS
Digital Video Data Inputs
Rx0+
Positive Differential Input Video Data (Channel 0)
Rx0–
Negative Differential Input Video Data (Channel 0)
Rx1+
Positive Differential Input Video Data (Channel 1)
Rx1–
Negative Differential Input Video Data (Channel 1)
Rx2+
Positive Differential Input Video Data (Channel 2)
Rx2–
Negative Differential Input Video Data (Channel 2)
These six pins receive three pairs of differential,
low voltage swing input pixel data from a digital
graphics transmitter.
Digital Video Clock Inputs
RxC+
Positive Differential Input Video Clock
RxC–
Negative Differential Input Video Clock
These two pins receive the differential, low voltage
swing input pixel clock from a digital graphics
transmitter.
Termination Control
RTERM
Internal Termination Set Pin
This pin is used to set the termination resistance
for all of the digital interface high-speed inputs. To
set, place a resistor of value equal to 10
× the desired
input termination resistance between this pin (Pin
53) and ground supply. Typically, the value of this
resistor should be 500
.
Outputs
DE
Data Enable Output
This pin outputs the state of data enable, (DE).
The AD9887 decodes DE from the incoming
stream of data. The DE signal will be HIGH dur-
ing active video and will be LOW while there is no
active video.
Power Supply
VD
Main Power Supply
It should be as quiet and as ltered as possible.
PVD
PLL Power Supply
It should be as quiet and as ltered as possible.
VDD
Outputs Power Supply
The power for the data and clock outputs. It can
run at 3.3 V or 2.5 V.
THEORY OF OPERATION (DIGITAL INTERFACE)
Capturing of the Encoded Data
The rst step in recovering the encoded data is to capture the
raw data. To accomplish this, the AD9887 employs a high-speed
Phase Locked Loop (PLL), to generate clocks capable of
oversampling the data at the correct frequencies. The data
capture circuitry continuously monitors the incoming data during
horizontal and vertical blanking times (when DE is low), and
independently selects the best sampling phase for each data
channel. The phase information is stored and used until the next
blanking period (one video line).
Data Frames
The digital interface data is captured in groups of 10 bits each,
called a data frame. During the active data period, each frame is
made up the nine encoded video data bits and one dc balancing
bit. The data capture block receives this data serially, but out-
puts each frame in parallel 10-bit words.
Special Characters
During periods of horizontal or vertical blanking time (when
DE is low), the digital transmitter will transmit special characters.
The AD9887 will receive these characters and use them to set the
video frame boundaries and the phase recovery loop for each
channel. There are four special characters that can be received.
They are used to identify the top, bottom, left side, and right side
of each video frame. The data receiver can differentiate these
special characters from active data because the special characters
have a different number of transitions per data frame.
Channel Resynchronization
The purpose of the channel resynchronization block is to resyn-
chronize the three data channels to a single internal data clock.
Coming into this block, all three data channels can be on differ-
ent phases of the three times oversampling PLL clock (0
°, 120°,
and 240
°). This block can resynchronize the channels from a
worst-case skew of one full input period (8.93 ns at 112 MHz).
Data Decoder
The data decoder receives frames of data and sync signals from
the data capture block (in 10-bit parallel words), and decodes
them into groups of eight RGB/YUV bits, two control bits, and
a data enable bit (DE).
OBSOLETE
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9887AKSZ-1001 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887AKSZ-140 | 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9887AKSZ-1401 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887AKSZ-170 | 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9887AKSZ-170 | 制造商:Analog Devices 功能描述:IC DUAL DISPLAY INTERFACE |
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