參數(shù)資料
型號(hào)： AD9887AKSZ-100
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/40頁(yè)
文件大?。?/td> 0K
描述： IC INTRFACE ANALOG/DVI 160-MQFP
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 圖形卡，VGA 接口
接口： 模擬和數(shù)字
電源電壓： 3.15 V ~ 3.45 V
封裝/外殼： 160-BQFP
供應(yīng)商設(shè)備封裝： 160-MQFP（28x28）
包裝： 托盤
安裝類型： 表面貼裝
REV. 0
AD9887
–27–
Table IX. Control Register Map (continued)
Read and
Hex
Write or
Default
Register
Address
Read Only
Bits
Value
Name
Function
12H
R/
W
7:0
0
*******
Active
Bit 7—AIO: Active Interface Override. If set to Logic 1, the user
Interface
can select the active interface via Bit 6. If set to Logic 0, the active
interface is selected via Bit 3 in Register 11H.
*0******
Bit 6—AIS: Active Interface Select. Logic 0 selects the analog inter-
face as active. Logic 1 selects the digital interface as active. Note:
The indicated interface will be active only if Bit 7 is set to Logic 1
or if both interfaces are active (Bits 6 or 7 and 4 = Logic 1 in
Register 11H.)
**0*****
Bit 5—Active Hsync Override. If set to Logic 1, the user can select
the Hsync to be used via Bit 4. If set to Logic 0, the active interface
is selected via Bit 2 in Register 11H.
***0****
Bit 4—Active Hsync Select. Logic 0 selects Hsync as the active
sync. Logic 1 selects Sync-on-Green as the active sync. Note: The
indicated Hsync will be used only if Bit 5 is set to Logic 1 or if
both syncs are active (Bits 6, 7 = Logic 1 in Register 11H.)
****0***
Bit 3—Active Vsync Override. If set to Logic 1, the user can select
the Vsync to be used via Bit 2. If set to Logic 0, the active interface
is selected via Bit 1 in Register 11H.
*****0**
Bit 2—Active Vsync Select. Logic 0 selects Raw Vsync as the
output Vsync. Logic 1 selects Sync Separated Vsync as the output
Vsync. Note: The indicated Vsync will be used only if Bit 3 is set
to Logic 1.
******0*
Bit 1—Coast Select. Logic 0 selects the coast input pin to be used for
the PLL coast. Logic 1 selects Vsync to be used for the PLL coast.
*******1
Bit 0—
PWRDN. Full Chip Power-Down, active low. (Logic 0 =
Full Chip Power-Down, Logic 1 = Normal.)
13H
R/
W
7:0
00100000
Sync
Sync Separator Threshold—Sets the number of clocks the sync
Separator
separator will count to before toggling high or low. This should be
Threshold
set to some number greater than the maximum Hsync or equaliza-
tion pulsewidth.
14H
R/
W
7:0
***1****
Control Bits
Bit 4—Must be set to 1 for proper operation.
****0***
Bit 3—Must be set to 0 for proper operation.
*****0**
Bit 2—Scan Enable. (Logic 0 = Not Enabled, Logic 1 = Enabled.)
******0*
Bit 1—Coast Polarity Override. (Logic 0 = Polarity determined by
chip, Logic 1 = Polarity set by Bit 6 in Register 0Fh.)
*******0
Bit 0—Hsync Polarity Override. (Logic 0 = Polarity determined by
chip, Logic 1 = Polarity set by Bit 7 in Register 0Fh.)
15H
RO
7:5
Polarity Status
Bit 7—Hsync Input Polarity Status. (Logic 1 = Active High,
Logic 0 = Active Low.)
Bit 6—Vsync Output Polarity Status. (Logic 0 = Active High,
Logic 1 = Active Low.)
Bit 5—Coast Input Polarity Status. (Logic 1 = Active High,
Logic 0 = Active Low.)
16H
R/
W
7:2
10111***
Control Bits 2
Bits [7:3]—Sync-On-Green Slicer Threshold
******1*
Bit 1—Must be set to 0 for proper operation.
17H
R/
W
7:0
00000000
Pre-Coast
Sets the number of Hsyncs that coast goes active prior to Vsync.
18H
R/
W
7:0
00000000
Post-Coast
Sets the number of Hsyncs that coast goes active following Vsync.
19H
R/
W
7:0
00000000
Test Register
Must be set to default for proper operation.
1AH
R/
W
7:0
11111111
Test Register
Must be set to 01000001 for proper operation.
OBSOLETE
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