- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16426 > AD9880/PCBZ (Analog Devices Inc)KIT EVALUATION AD9880 PDF資料下載
參數(shù)資料
| 型號： | AD9880/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 46/64頁 |
| 文件大小： | 0K |
| 描述： | KIT EVALUATION AD9880 |
| 標準包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，視頻處理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9880 |
| 主要屬性： | 模擬和 HDMI/DVI 雙路顯示器端口 |
| 次要屬性： | 自動偏移，色域轉(zhuǎn)換器，RGB 和 YCbCr 輸出格式 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD9880KSTZ-150-ND - IC INTERFACE/HDMI 150MHZ 100LQFP AD9880KSTZ-100-ND - IC INTERFACE/HDMI 100MHZ 100LQFP |
| 其它名稱： | Q5281026 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁當前第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
AD9880
Rev. 0 | Page 50 of 64
Table 76.
PLL_N [2:0]
MCLK Divide Value
0
/1
1
/2
2
/3
3
/4
4
/5
5
/6
6
/7
7
/8
0x58
3
N_CTS_Disable
This bit makes it possible to prevent the N/CTS packet
on the link from writing to the N and CTS registers.
0x58
2-0
MCLK fs_N
These bits control the multiple of 128 fs used for
MCLK out.
Table 77.
MCLK fs_N [2:0]
fs Multiple
0
128
1
256
2
384
3
512
4
640
5
768
6
896
7
1024
0x59
6
MDA/MCL PU Disable
This bit disables the inter MDA/MCL pull-ups.
0x59
5
CLK Term O/R
This bit allows for overriding during power down.
0 = auto, 1 = manual.
0x59
4
Manual CLK Term
This bit allows normal clock termination or
disconnects this. 0 = normal, 1 = disconnected.
0x59
2
FIFO Reset UF
This bit resets the audio FIFO if underflow is detected.
0x59
1
FIFO Reset OF
This bit resets the audio FIFO if overflow is detected.
0x59
0
MDA/MCL Three-State
This bit three-states the MDA/MCL lines to allow in-
circuit programming of the EEPROM.
0x5A
6-0
Packet Detect
This register indicates if a data packet in specific
sections has been detected. These seven bits are
updated if any specific packet has been received since
last reset or loss of clock detect. Normal is 0x00.
Table 78.
Packet Detect Bit
Packet Detected
0
AVI infoframe
1
Audio infoframe
2
SPD infoframe
3
MPEG Source infoframe
4
ACP packets
5
ISRC1 packets
6
ISRC2 packets
0x5B
3
HDMI Mode
0 = DVI, 1 = HDMI.
0x5E
7-6
Channel Status Mode
0x5E
5-3
PCM Audio Data
0x5E
2
Copyright Information
0x5E
1
Linear PCM Identification
0x5E
0
Use of Channel Status Block
0x5F
7-0
Channel Status Category Code
0x60
7-4
Channel Number
0x60
3-0
Source Number
0x61
5-4
Clock Accuracy
0x61
3-0
Sampling Frequency
Table 79.
Code
Frequency (kHz)
0x0
44.1
0x2
48
0x3
32
0x8
88.2
0xA
96
0xC
176.4
0xE
192
0x62
3-0
Word Length
0x7B
7-0
CTS (Cycle Time Stamp) (19-12)
These are the most significant 8 bits of a 20-bit word
used in the 20-bit N term in the regeneration of the
audio clock.
0x7C
7-0
CTS (11-4)
0x7D
7-4
CTS (3-0)
0x7D
3-0
N (19-16)
These are the most significant 4 bits of a 20-bit word
used along with the 20-bit CTS term to regenerate the
audio clock.
0x80
AVI Infoframe Version
0x81
6-5
Y [1:0]
This register indicates whether data is RGB, 4:4:4 or
4:2:2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S01-02-R | SOLDER SLEEVE IMMERS RESIS .650" |
| ILSB1206ER180K | INDUCTOR 18UH 10% 1206 |
| 242489-000 | CWT-3811 |
| VI-J10-EX | CONVERTER MOD DC/DC 5V 75W |
| GEC20DRYH-S734 | CONN EDGECARD 40POS DIP .100 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9880XSTZ-100 | 制造商:Analog Devices 功能描述:IC, ANALOG/HDMI DUAL DISPLAY INTERFACE, PQFP100 |
| AD9882 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9882/PCB | 制造商:Analog Devices 功能描述:DUAL INTRFC FOR FLAT PNL DISPLAY 100LQFP - Bulk |
| AD9882A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9882A/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
發(fā)布緊急采購，3分鐘左右您將得到回復。