參數(shù)資料
型號(hào)： AD9788BSVZRL
廠商： Analog Devices Inc
文件頁數(shù)： 48/64頁
文件大?。?/td> 0K
描述： IC DAC 16BIT 800MSPS 100TQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源： Powering the AD9788 Using ADP2105 for Increased Efficiency (CN0141)
標(biāo)準(zhǔn)包裝： 1,000
系列： TxDAC®
位數(shù)： 16
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 450mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電流，單極；4 電流，雙極
采樣率（每秒）： 800M
AD9785/AD9787/AD9788
Rev. A | Page 52 of 64
POWER DISSIPATION
Figure 74 through Figure 78 detail the power dissipation of the
AD9785/AD9787/AD9788 under a variety of operating conditions.
All of the graphs are taken with data being supplied to both the
I and Q channels. The power consumption of the device does
not vary significantly with changes in the modulation mode or
analog output frequency. Graphs of the total power dissipation
are shown along with the power dissipation of the DVDD18,
DVDD33, and CVDD18 supplies.
The power dissipation of the AVDD33 supply rail is independent
of the digital operating mode and sample rate. The current drawn
from the AVDD33 supply rail is typically 51 mA (182 mW) when
the full-scale current of the I and Q DACs is set to the nominal
value of 20 mA. Changing the full-scale current directly impacts
the supply current drawn from the AVDD33 rail. For example,
if the full-scale current of the I DAC and the Q DAC is changed
to 10 mA each, the AVDD33 supply current drops to 31 mA.
0
300
250
fDATA (MSPS)
PO
W
E
R
(mW
)
1800
1600
1400
1200
1000
800
600
400
200
50
100
150
200
07
09
8-
0
35
1×
1× NCO
2×
2× NCO
4×
4× NCO
8×
8× NCO
Figure 74. Power Dissipation, I and Q Data, Dual DAC Mode
0
300
250
fDATA (MSPS)
PO
WER
(
m
W
)
1400
1200
1000
800
600
400
200
50
100
150
200
07
09
8-
0
36
1×
1× NCO
2×
2× NCO
4×
4× NCO
8×
8× NCO
Figure 75. Power Dissipation, Digital 1.8 V Supply, I and Q Data,
Dual DAC Mode
0
300
250
fDATA (MSPS)
P
O
WE
R
(
m
W)
70
60
50
40
30
20
10
50
100
150
200
07
09
8-
03
7
1×
1× NCO
2×
2× NCO
4×
4× NCO
8×
8× NCO
Figure 76. Power Dissipation, Digital 3.3 V Supply, I and Q Data,
Dual DAC Mode
0
300
250
fDATA (MSPS)
PO
W
E
R
(mW
)
120
100
80
60
40
20
50
100
150
200
07
09
8-
0
38
1×
1× NCO
2×
2× NCO
4×
4× NCO
8×
8× NCO
Figure 77. Power Dissipation, Clock 1.8 V Supply, I and Q Data,
Dual DAC Mode
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