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參數(shù)資料
| 型號： | AD9788BSVZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 800MSPS 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 設(shè)計資源： | Powering the AD9788 Using ADP2105 for Increased Efficiency (CN0141) |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | TxDAC® |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 450mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 800M |
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AD9785/AD9787/AD9788
Rev. A | Page 32 of 64
The frequency tuning word (FTW) register comprises four bytes located at Address 0x0A.
Table 20. Frequency Tuning Word (FTW) Register
Address
Bit
Name
Description
0x0A
[31:0]
Frequency Tuning
Word [31:0]
These bits make up the frequency tuning word applied to the NCO phase accumulator.
See the Numerically Controlled Oscillator section for details.
The phase control register (PCR) comprises four bytes located at Address 0x0B.
Table 21. Phase Control Register (PCR)
Address
Bit
Name
Description
0x0B
[31:26]
Reserved
Reserved for future use.
[25:16]
Phase Correction
Word [9:0]
These bits are the 10-bit phase correction word.
[15:0]
NCO Phase Offset
Word [15:0]
These bits are the 16-bit NCO phase offset word. See the Numerically Controlled Oscillator
section for details.
The amplitude scale factor (ASF) register comprises three bytes located at Address 0x0C.
Table 22. Amplitude Scale Factor (ASF) Register
Address
Bit
Name
Description
0x0C
[23:18]
Reserved
Reserved for future use.
[17:9]
Q DAC Amplitude
Scale Factor [8:0]
These bits are the 9-bit Q DAC amplitude scale factor. The bit weighting is MSB = 21,
LSB = 27, which yields a multiplier range of 0 to 3.9921875. Note that by setting the gain to
1.0 (0x080), the gain block is bypassed. This changes the latency of the signal. Therefore, in
systems using quadrature signals, either both I and Q scale factors should be bypassed or
both should have gains set to a value other than 1.0.
[8:0]
I DAC Amplitude
Scale Factor [8:0]
These bits are the 9-bit I DAC amplitude scale factor. The bit weighting is MSB = 21,
LSB = 27, which yields a multiplier range of 0 to 3.9921875.
The output offset (OOF) register comprises four bytes located at Address 0x0D.
Table 23. Output Offset (OOF) Register
Address
Bit
Name
Description
0x0D
[31:16]
Q DAC Offset [15:0]
These bits are the 16-bit Q DAC offset factor. The LSB bit weight is 20.
[15:0]
I DAC Offset [15:0]
These bits are the 16-bit I DAC offset factor. The LSB bit weight is 20.
The version register (VR) comprises two bytes located at Address 0x0E and is read only.
Table 24. Version Register (VR)
Address
Bit
Name
Description
0x0E
[15:8]
Reserved
Reserved for future use.
[7:0]
Version ID
These bits read back the current version of the product.
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