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參數(shù)資料
| 型號： | AD9788BSVZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 800MSPS 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 設(shè)計資源： | Powering the AD9788 Using ADP2105 for Increased Efficiency (CN0141) |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | TxDAC® |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 450mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 800M |
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AD9785/AD9787/AD9788
Rev. A | Page 28 of 64
The multichip synchronization register (MSCR) comprises four bytes located at Address 0x03.
Table 13. Multichip Synchronization Register (MSCR)
Address
Bit
Name
Description
0x03
[31:27]
Correlate Threshold
[4:0]
Sets the threshold for determining if the received synchronization data can be demodulated
accurately. A smaller threshold value makes the demodulator more noise immune; however,
the system becomes more susceptible to false locks (or demodulation errors).
[26]
SYNC_I enable
0: Default. The synchronization receive logic is disabled.
1: The synchronization receive logic is enabled.
[25]
SYNC_O enable
0: Default. The output synchronization pulse generation logic is disabled.
1: The output synchronization pulse generation logic is enabled.
[24]
Set low
This bit should always be set low.
[23:19]
SYNC_I Delay [4:0]
This value programs the value of the delay line of the SYNC_I signal. The delay line resolution
is 80 ps per step.
00000: nominal delay
00001: adds 80 ps delay to SYNC_I
00010: adds 160 ps delay to SYNC_I
…
11111: adds 2480 ps delay to SYNC_I
[18]
Sync error check mode
Specifies the synchronization pulse error check mode.
0: Manual error check
1: Automatic continuous error check
[17]
Set low
This bit should always be set low.
[16]
DATACLK input
0: Default. Slave mode is disabled.
1: Slave mode is enabled. Pin 37 functions as an input for the DATACLK signal, called DCI
(DATACLK input) in this mode. Depending on the state of Bit 1 in the DSCR register (Address
0x02), the sampling edge (where the data is latched into the AD9785/AD9787/AD9788) can
be programmed to be aligned with either the rising or falling edge of DCI. This mode can
only be used with 4× or 8× interpolation.
[15:11]
SYNC_O Delay [4:0]
This value programs the value of the delay line of the SYNC_O signal. The delay of SYNC_O is
relative to REFCLK. The delay line resolution is 80 ps per step.
00000: nominal delay
00001: adds 80 ps delay to SYNC_O
00010: adds 160 ps delay to SYNC_O
…
11111: adds 2480 ps delay to SYNC_O
[10]
Set high
This bit should always be set high.
[9]
SYNC_O polarity
0: Default. SYNC_O changes state on the rising edge of DACCLK.
1: SYNC_O is generated on the falling edge of DACCLK.
[8]
Sync loopback enable
0: Default. The AD9785/AD9787/AD9788 are not operating in internal loopback mode.
1: If the SYNC_O enable and Sync loopback enable bits are set, the AD9785/AD9787/AD9788
are operating in a mode in which the internal synchronization pulse of the device is used at
the multichip receiver logic and the SYNC_I+ and SYNC_I input pins are ignored. For proper
operation of the loopback synchronization mode, the synchronization driver enable and
sync enable bits must be set.
[7:4]
Clock State [3:0]
This value determines the state of the internal clock generation state machine upon
synchronization.
[3:0]
Sync Timing Margin
[3:0]
These bits are the synchronization window delay word. These bits are don’t care if the
synchronization driver enable bit is cleared.
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