- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1894 > AD9788BSVZRL (Analog Devices Inc)IC DAC 16BIT 800MSPS 100TQFP PDF資料下載
參數(shù)資料
| 型號： | AD9788BSVZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 800MSPS 100TQFP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 設計資源： | Powering the AD9788 Using ADP2105 for Increased Efficiency (CN0141) |
| 標準包裝： | 1,000 |
| 系列： | TxDAC® |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 450mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應商設備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 800M |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
AD9785/AD9787/AD9788
Rev. A | Page 29 of 64
The PLL control (PLLCTL) register comprises three bytes located at Address 0x04. These bits are routed directly to the periphery of the
digital logic. No digital functionality within the main digital block is required.
Table 14. PLL Control (PLLCTL) Register
Address
Bit
Name
Description
0x04
[23:21]
VCO Control Voltage
[2:0]
000 to 111, proportional to voltage at VCO, control voltage input (readback only). A value of
011 indicates that the VCO control voltage is centered.
[20:16]
PLL Loop Bandwidth
[4:0]
These bits control the bandwidth of the PLL filter. Increasing the value lowers the loop
bandwidth. Set to 01111 for optimal performance.
[15]
PLL enable
0: Default. With PLL off, the DAC sample clock is sourced directly by the REFCLK input.
1: With PLL on, the DAC clock is synthesized internally from the REFCLK input via the PLL
clock multiplier. See the Clock Multiplication section for details.
[14:13]
PLL VCO Divisor [1:0]
Sets the value of the VCO output divider, which determines the ratio of the VCO output
frequency to the DAC sample clock frequency, fVCO/fDACCLK.
00: fVCO/fDACCLK = 1
01: fVCO/fDACCLK = 2
10: fVCO/fDACCLK = 4
11: fVCO/fDACCLK = 8
[12:11]
PLL Loop Divisor [1:0]
Sets the value of the DACCLK divider, which determines the ratio of the DAC sample clock
frequency to the REFCLK frequency, fDACCLK/fREFCLK.
00: fDACCLK/fREFCLK = 2
01: fDACCLK/fREFCLK = 4
10: fDACCLK/fREFCLK = 8
11: fDACCLK/fREFCLK = 16
[10:8]
PLL Bias [2:0]
These bits control the VCO bias current. Set to 011 for optimal performance.
[7:2]
PLL Band Select [5:0]
These bits set the operating frequency of the VCO. For further details, refer to Table 35.
[1:0]
PLL VCO Drive [1:0]
These bits control the signal strength of the VCO output. Set to 11 for optimal performance.
The I DAC control register comprises two bytes located at Address 0x05. These bits are routed directly to the periphery of the digital
logic. No digital functionality within the main digital block is required.
Table 15. I DAC Control Register
Address
Bit
Name
Description
0x05
[15]
I DAC sleep
0: Default. If the I DAC sleep bit is cleared, the I DAC is active.
1: If the I DAC sleep bit is set, the I DAC is inactive and enters a low power state.
[14]
I DAC power-down
0: Default. If the I DAC power-down bit is cleared, the I DAC is active.
1: If the I DAC power-down bit is set, the I DAC is inactive and enters a low power state.
[13:10]
Reserved
Reserved for future use.
[9:0]
I DAC gain
adjustment
These bits are the I DAC gain adjustment bits.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9806KSTZ | IC CCD SIGNAL PROC 10BIT 48LQFP |
| AD9814JR | IC CCD SIGNAL PROC 14BIT 28-SOIC |
| AD9823KRUZRL7 | IC CDS FOR DGTL CAMERA 14-TSSOP |
| AD9824KCPZRL | IC CCD SIGNAL PROC 14BIT 48LFCSP |
| AD9826KRSZRL | IC IMAGE SGNL PROC 16BIT 28-SSOP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9788-DPG2-EBZ | 功能描述:BOARD EVALUATION FOR AD9788 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9788-EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD9788 制造商:Analog Devices 功能描述:DUAL 16B, D-A CONVERTER - Bulk 制造商:Analog Devices 功能描述:Digital to Analog Eval. Board |
| AD9788MOD-EBZ | 制造商:Analog Devices 功能描述:DUAL 12-/14-/16-BIT 800 MSPS DAC WITH LOW POWER 32-BIT COMPLEX NCO 制造商:Analog Devices 功能描述:DUAL 16B, D-A CONVERTER - Bulk |
| AD9789BBC | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 14 Bit 2.5 GSPS D-A Converter RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| AD9789BBCRL | 制造商:Analog Devices 功能描述:QAM Encoder/Interpolator/Upconverter 164-Pin CSP-BGA T/R 制造商:Analog Devices 功能描述:QAM ENCODER/INTERPOLATOR/UPCNVRTR 164CSPBGA - Tape and Reel 制造商:Analog Devices 功能描述:IC DAC 14BIT 2.4GSPS 4CH 164BGA 制造商:Analog Devices Inc. 功能描述:Digital to Analog Converters - DAC 14 Bit 2.5 GSPS D-A Converter 制造商:Analog Devices Inc. 功能描述:Digital to Analog Converters - DAC 14B 2400MSPS RF w/ 4CH Signal Process 制造商:Analog Devices 功能描述:CONVERTER - DAC |
發(fā)布緊急采購，3分鐘左右您將得到回復。