參數(shù)資料
型號(hào)： AD9788BSVZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/64頁(yè)
文件大?。?/td> 0K
描述： IC DAC 16BIT 800MSPS 100TQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源： Powering the AD9788 Using ADP2105 for Increased Efficiency (CN0141)
標(biāo)準(zhǔn)包裝： 1,000
系列： TxDAC®
位數(shù)： 16
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 450mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電流，單極；4 電流，雙極
采樣率（每秒）： 800M
AD9785/AD9787/AD9788
Rev. A | Page 26 of 64
The digital control (DCTL) register comprises two bytes located at Address 0x01.
Table 11. Digital Control (DCTL) Register
Address
Bit
Name
Description
0x01
[15]
Reserved
Reserved for future use.
[14]
Clear phase
accumulator
0: Default. The feature that clears the NCO phase accumulator is inactive. The phase
accumulator operates as normal.
1: The NCO phase accumulator is held in the reset state until this bit is cleared.
[13]
PN code sync
enable
0: PN code synchronization mode is disabled.
1: PN code synchronization mode is enabled. See the Device Synchronization section for
details.
[12]
Sync mode select
0: Selects pulse mode synchronization.
1: Selects PN code synchronization. See the Device Synchronization section for details.
[11]
Pulse sync enable
0: Pulse mode synchronization is disabled.
1: Pulse mode synchronization is enabled. See the Device Synchronization section for details.
[10]
Reserved
Reserved for future use.
[9]
Inverse sinc
enable
0: Default. The inverse sinc filter is bypassed.
1: The inverse sinc filter is enabled and operational.
[8]
DATACLK
output enable
0: Data clock pin is disabled.
1: Default. The output data clock pin is active (configured as an output).
[7:6]
Interpolation
Factor [1:0]
Specifies the filter interpolation rate where:
00: 1× interpolation
01: 2× interpolation
10: 4× interpolation
11: 8× interpolation
[5]
Data format
0: Default. The incoming data is expected to be twos complement.
1: The incoming data is expected to be offset binary.
[4]
Single-port mode
0: Default. When the single-port bit is cleared, I/Q data is sampled simultaneously on the P1D
and P2D input ports. Specifically, I data is registered from the P1D[15:0] pins and Q data is
registered from the P2D[15:0] pins.
1: When the single-port bit is set, I/Q data is sampled in a serial word fashion on the P1D input
port. In this mode, the I/Q data is sampled into the part at twice the I/Q sample rate.
[3]
Real mode
0: Default. Logic 0 is the inactive state for this bit.
1: When the real mode bit is set, the Q path logic after modulation and phase compensation is
disabled.
[2]
IQ select invert
0: Default. When the IQ Select Invert bit is cleared, a Logic 1 on the TXENABLE pin indicates
I data, and a Logic 0 on the TXENABLE pin indicates Q data, if the user is employing a
continuous timing style on the TXENABLE pin.
1: When the IQ Select Invert bit is set, a Logic 1 on the TXENABLE pin indicates Q data, and a
Logic 0 on the TXENABLE pin indicates I data, if the user is employing a continuous timing
style on the TXENABLE pin.
[1]
Q first (data
pairing)
0: Default. When the Q first bit is cleared, the I/Q data pairing is nominal, that is, the I data
precedes the Q data in the assembly of the I/Q data pair. As such, data input to the device as
I0, Q0, I1, Q1 . . . In, Qn is paired as follows: (I0/Q0), (I1/Q1) … (In/Qn).
1: When the Q first bit is set, the I/Q data pairing is altered such that the I data is paired with
the previous Q data. As such, data input to the device as I0, Q0, I1, Q1, I2, Q2, I3, Q3 . . . In, Qn is
paired as follows: (I1/Q0), (I2/Q1), (I3/Q2) … (In + 1/Qn).
[0]
Modulator gain
control
0: Default. No gain scaling is applied to the NCO input to the internal digital modulator.
1: Gain scaling of 0.5 is applied to the NCO input to the modulator. This can eliminate
saturation of the modulator output for some combinations of data inputs and NCO signals.
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