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參數(shù)資料
| 型號： | AD9772 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14-Bit,150 MSPS T×DAC+TM with 2× Interpolation Filter(單電源,過采樣,14位D/A轉(zhuǎn)換器) |
| 中文描述： | 14位，150 MSPS的DAC的商標(biāo)厚× 2 ×插值濾波器（單電源，過采樣，14位的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 7/30頁 |
| 文件大?。?/td> | 341K |
| 代理商： | AD9772 |
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REV. 0
AD9772
–7–
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Description
1, 2, 19, 20
3
4–15
16
17
18
DCOM
DB13
DB12–DB1
DB0
MOD0
MOD1
Digital Common.
Most Significant Data Bit (MSB).
Data Bits 1–12.
Least Significant Data Bit (LSB).
Invokes digital high-pass filter response (i.e., “half-wave” digital mixing mode). Active High.
Invokes “zero-stuffing” mode. Active High. Note, “quarter-wave” digital mixing occurs with
MOD0 also set HIGH.
No Connect, Leave Open.
Digital Supply Voltage (+2.7 V to +3.6 V).
Phase Lock Loop Lock Signal when PLL clock multiplier is enabled. High indicates PLL is
locked to input clock. Provides 1
×
clock output when PLL clock multiplier is disabled. Maxi-
mum fanout is one (i.e., <10 pF).
Resets internal divider by bringing momentarily high when PLL is disabled to synchronize inter-
nal 1
×
clock to the input data and/or multiple AD9772 devices.
DIV1 along with DIV0 sets the PLL’s prescaler divide ratio (refer to Table III.)
Noniverting input to differential clock. Bias to midsupply (i.e., CLKVDD/2).
Inverting input to differential clock. Bias to midsupply (i.e., CLKVDD/2).
Clock Input Common.
Clock Input Supply Voltage (+2.7 V to +3.6 V).
Phase Lock Loop Common.
Phase Lock Loop (PLL) Supply Voltage (+2.7 V to +3.6 V). To disable PLL clock multiplier,
connect PLLVDD to PLLCOM.
PLL Loop Filter Node.
Power-Down Control Input. Active High. Connect to ACOM if not used.
Analog Common.
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal
reference.
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie
REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie
REFLO to ACOM). Requires 0.1
μ
F capacitor to ACOM when internal reference activated.
Full-Scale Current Output Adjust.
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
DAC Current Output. Full-scale current when all data bits are 1s.
Analog Supply Voltage (+2.7 V to +3.6 V).
23, 24
21, 22, 47, 48
25
NC
DVDD
PLLLOCK
26
RESET
27, 28
29
30
31
32
33
34
DIV1, DIV0
CLK+
CLK–
CLKCOM
CLKVDD
PLLCOM
PLLVDD
35
36
37, 41, 44
38
LPF
SLEEP
ACOM
REFLO
39
REFIO
40
42
43
45, 46
FSADJ
IOUTB
IOUTA
AVDD
PIN CONFIGURATION
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
TOP VIEW
(Not to Scale)
SLEEP
LPF
PLLVDD
PLLCOM
CLKVDD
CLKCOM
CLK–
CLK+
DIV0
DIV1
RESET
PLLLOCK
DCOM
DCOM
(MSB) DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
NC = NO CONNECT
AD9772
D
D
A
A
A
I
I
A
F
R
R
A
D
D
D
(
M
M
D
D
D
D
N
N
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| AD9773EB | 12-Bit, 160 MSPS 2】/4】/8】 Interpolating Dual TxDAC+ D/A Converter |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9772A | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 160 MSPS TxDAC+ with 2x Interpolation Filter |
| AD9772AAST | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 14-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:14BIT 160 MSPS TXDAC+ W/2X INTERPOLATION - Tape and Reel 制造商:Analog Devices 功能描述:Digital-Analog Converter IC Number of Bi |
| AD9772AASTRL | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 14-bit 48-Pin LQFP T/R |
| AD9772AASTZ | 功能描述:IC DAC 14BIT 160MSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD9772AASTZRL | 功能描述:IC DAC 14BIT 160MSPS 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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