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參數(shù)資料
| 型號： | AD9772 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14-Bit,150 MSPS T×DAC+TM with 2× Interpolation Filter(單電源,過采樣,14位D/A轉(zhuǎn)換器) |
| 中文描述： | 14位，150 MSPS的DAC的商標厚× 2 ×插值濾波器（單電源，過采樣，14位的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 11/30頁 |
| 文件大小： | 341K |
| 代理商： | AD9772 |
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REV. 0
AD9772
–11–
FUNCTIONAL DESCRIPTION
Figure 22 shows a simplified block diagram of the AD9772.
The AD9772 is a complete, 2
×
oversampling, 14-bit DAC that
includes a 2
×
interpolation filter, a phase-locked loop (PLL)
clock multiplier and a 1.20 V bandgap voltage reference. While
the AD9772’s digital interface can support input data rates as
high as 150 MSPS, its internal DAC can operate up to 400 MSPS,
thus providing direct IF conversion capabilities. The 14-bit
DAC provides two complementary current outputs whose full-
scale current is determined by an external resistor. The AD9772
features a flexible, low jitter, differential clock input providing
excellent noise rejection while accepting a sine wave input. An
on-chip PLL clock multiplier produces all of the necessary
synchronized clocks from an external reference clock source.
Separate supply inputs are provided for each functional block to
ensure optimum noise and distortion performance. A SLEEP
mode is also included for power savings.
14-BIT DAC
ZERO
MUX
3
FIR
INTE2
FILTER
TLATCHES
CAND MODE SELECT
2
3
/4
3
CONMUX
FILTER
CONTROL
1
3
/2
3
1
3
PLL CLOCK
MULTIPLIER
+1.2V REFERENCE
AD9772
CLKCOM CLKVDD
MOD0 MOD1
RESET
PLLLOCK
DIV0 DIV1
CLK+
CLK–
(DB1IDATA
SLEEP
DCOM
DVDD
ACOM
AVDD
REFLO
PLLCOM
LPF
PLLVDD
IOUTA
IOUTB
REFIO
FSADJ
Figure 22. Functional Block Diagram
Preceding the 14-bit DAC is a 2
×
digital interpolation filter that
can be configured for a low pass (i.e., baseband mode) or high
pass (i.e., direct IF mode) response. The input data is latched
into the edge-triggered input latches on the rising edge of the
differential input clock as shown in Figure 1a and then interpo-
lated by a
factor of two
by the digital filter. For traditional base-
band applications, the 2
×
interpolation filter has a low pass
response. For direct IF applications, the filter’s response can be
converted into a high pass response to extract the higher image.
The output data of the 2
×
interpolation filter can update the
14-bit DAC directly or undergo a “zero-stuffing” process to
increase the DAC update rate by another
factor of two
. This
action enhances the relative signal level and passband flatness of
the higher images.
DIGITAL MODES OF OPERATION
The AD9772 features four different digital modes of operation
controlled by the digital inputs, MOD0 and MOD1. MOD0
controls the 2
×
digital filter’s response (i.e., low pass or high
pass), while MOD1 controls the “zero-stuffing” option. The
selected mode as shown in Table II will depend on whether the
application requires the reconstruction of a baseband or IF signal.
Table II. Digital Modes
Digital
Mode
Digital
Filter
Zero-
Stuffing
MOD0
MOD1
Baseband
Baseband
Direct IF
Direct IF
0
0
1
1
0
1
0
1
Low
Low
High
High
No
Yes
No
Yes
Applications requiring the highest dynamic range over a wide
bandwidth should consider operating the AD9772 in a baseband
mode. Note, the “zero-stuffing” option can also be used in this
mode although the ratio of signal to image power will be re-
duced. Applications requiring the synthesis of IF signals should
consider operating the AD9772 in a Direct IF mode. In this
case, the “zero-stuffing” option should be considered when
synthesizing and selecting IFs beyond the input data rate, f
DATA
.
If the reconstructed IF falls below f
DATA
, the “zero-stuffing”
option may or may not be beneficial. Note, the dynamic range
(i.e., SNR/SFDR) is also optimized by disabling the PLL Clock
Multiplier (i.e., PLLVDD to PLLCOM) and using an external
low jitter clock source operating at the DAC update rate, f
DAC
.
2
3
Interpolation Filter Description
The 2
×
interpolation filter is based on a 43-tap half-band sym-
metric FIR topology that can be configured for a low or high
pass response, depending on state of the MOD0 control input.
The low pass response is selected with MOD0 LOW while the
high pass response is selected with MOD0 HIGH. The low pass
frequency and impulse response of the half-band interpolation
filter are shown in Figures 2a and 2b, while Table I lists the
idealized filter coefficients. Note, a FIR filter’s impulse response
is also represented by its idealized filter coefficients.
The 2
×
interpolation filter essentially multiplies the input data
rate to the DAC by a factor of two, relative to its original input
data rate, while simultaneously reducing the magnitude of the
1st image associated with the original input data rate occurring
at f
DATA
– f
FUNDAMENTAL
. Note, as a result of the 2
×
interpola-
tion, the digital filter’s frequency response is uniquely defined
over its Nyquist zone of dc to f
DATA
, with mirror images occur-
ring in adjacent Nyquist zones.
The benefits of an interpolation filter are clearly seen in Figure
23, which shows an example of the frequency and time domain
representation of a discrete time sine wave signal before and
after it is applied to the 2
×
digital interpolation filter in a low
pass configuration. Images of the sine wave signal appear around
multiples of the DAC’s input data rate (i.e., f
DATA
) as predicted
by sampling theory. These undesirable images will also appear
at the output of a reconstruction DAC, although attenuated by
the DAC’s sin(x)/x roll-off response.
In many bandlimited applications, the images from the recon-
struction process must be suppressed by an analog filter follow-
ing the DAC. The complexity of this analog filter is typically
determined by the proximity of the desired fundamental to the
first image and the required amount of image suppression. Add-
ing to the complexity of this analog filter may be the require-
ment of compensating for the DAC’s sin(x)/x response.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9772A | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 160 MSPS TxDAC+ with 2x Interpolation Filter |
| AD9772AAST | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 14-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:14BIT 160 MSPS TXDAC+ W/2X INTERPOLATION - Tape and Reel 制造商:Analog Devices 功能描述:Digital-Analog Converter IC Number of Bi |
| AD9772AASTRL | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 14-bit 48-Pin LQFP T/R |
| AD9772AASTZ | 功能描述:IC DAC 14BIT 160MSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD9772AASTZRL | 功能描述:IC DAC 14BIT 160MSPS 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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