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參數(shù)資料
| 型號： | AD9772 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14-Bit,150 MSPS T×DAC+TM with 2× Interpolation Filter(單電源,過采樣,14位D/A轉(zhuǎn)換器) |
| 中文描述： | 14位，150 MSPS的DAC的商標(biāo)厚× 2 ×插值濾波器（單電源，過采樣，14位的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 24/30頁 |
| 文件大?。?/td> | 341K |
| 代理商： | AD9772 |
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REV. 0
AD9772
–24–
AD9772 EVALUATION BOARD
The AD9772-EB is an evaluation board for the AD9772 TxDAC.
Careful attention to layout and circuit design, combined with
prototyping area, allows the user to easily and effectively evalu-
ate the AD9772 in different modes of operation.
Referring to Figures 54 and 55, the AD9772’s performance can
be evaluated differentially or single-ended using a transformer,
differential amplifier, or directly coupled output. To evaluate
the output differentially using the transformer, remove jumpers
JP12 and JP13 and monitor the output at J6 (IOUT). To evalu-
ate the output differentially, remove the transformer (T2) and
install jumpers JP12 and JP13. The output of the amplifier can
be evaluated at J13 (AMPOUT). To evaluate the AD9772
single-ended and directly coupled, remove the transformer and
jumpers (JP12 and JP13) and install resistors R16 or R17 with
0
.
The digital data to the AD9772 comes across a ribbon cable
which interfaces to a 40-pin IDC connector. Proper termina-
tion or voltage scaling can be accomplished by installing RN2
and/or RN3 SIP resistor networks. The 22
DIP resistor net-
work, RN1, must be installed and helps reduce the digital data
edge rates. A single-ended CLOCK input can be supplied via
the ribbon cable by installing JP8 or more preferably via the
SMA connector, J3 (CLOCK). If the CLOCK is supplied by J3,
the AD9772 can be configured for a differential clock interface
by installing jumpers JP1 and configuring JP2, JP3, and JP9 for
the DF position. To configure the AD9772 clock input for a
single-ended clock interface, remove JP1 and configure JP2, JP3
and JP9 for the SE position.
The AD9772’s PLL clock multiplier can be disabled by config-
uring jumper JP5 for the L position. In this case, the user must
supply a clock input at twice (2
×
)the data rate via J3 (CLOCK).
The 1
×
clock is made available on SMA connector, J1
(PLLLOCK) and should be used to trigger a pattern generator
directly or via a programmable pulse generator. Note, PLLLOCK
is capable of providing a 0 V to 0.85 V output into a 50
load.
To enable the PLL clock multiplier, JP5 must be configured for
the H position. In this case, the clock may be supplied via the
ribbon cable (i.e., JP8 installed) or J3 (CLOCK). The divide-
by-N ratio can be set by configuring JP6 (DIV0) and JP7 (DIV1).
The AD9772 can be configured for Baseband or Direct IF Mode
operation by configuring jumpers JP11 (MOD0) and JP10
(MOD1). For baseband operation, JP10 and JP11 should be
configured in the L position. For direct IF operation, JP10 and
JP11 should be configured in the H position. For direct IF
operation without “zero-stuffing,” JP11 should be configured in
the H position while JP10 should be configured in the low position.
The AD9772’s voltage reference can be enabled or disabled via
JP4 (EXT REF IN). To enable the reference, configure JP in
the INT position. A voltage of approximately 1.2 V will appear
at the TP6 (REFIO) test point. To disable the internal refer-
ence, configure JP4 in the EXT position and drive TP6 with an
external voltage reference. Lastly, the AD9772 can be placed in
the SLEEP mode by driving the TP11 test point with logic level
HIGH input signal.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9772A | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 160 MSPS TxDAC+ with 2x Interpolation Filter |
| AD9772AAST | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 14-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:14BIT 160 MSPS TXDAC+ W/2X INTERPOLATION - Tape and Reel 制造商:Analog Devices 功能描述:Digital-Analog Converter IC Number of Bi |
| AD9772AASTRL | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 14-bit 48-Pin LQFP T/R |
| AD9772AASTZ | 功能描述:IC DAC 14BIT 160MSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD9772AASTZRL | 功能描述:IC DAC 14BIT 160MSPS 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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