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參數(shù)資料
| 型號(hào)： | AD9734 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14/12/10-Bit, 1200 MSPS D/A Converters |
| 中文描述： | 14/12/10-Bit，1200 MSPS的D / A轉(zhuǎn)換 |
| 文件頁(yè)數(shù)： | 4/42頁(yè) |
| 文件大?。?/td> | 934K |
| 代理商： | AD9734 |
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AD9736/AD9735/AD9734
Preliminary Technical Data
DIGITAL SPECIFICATIONS
1
Rev. PrJ | Page 4 of 42
(VDDA33 = VDDD33 = 3.3 V, VDDA18 = VDDD18 = VDDCLK = 1.8 V, MAXIMUM SAMPLE RATE, FS = 20MA,
1X MODE, 25 OHM 1% BALANCED LOAD, UNLESS OTHERWISE NOTED)
AD9736,35,34
Parameter
Temp
Test Level
Min
Typ
Max
Unit
Input voltage range, Via or Vib
Input differential threshold
Input differential hysteresis
Receiver differential input impedance
LVDS input rate
LVDS data Bit Error Rate
Input voltage range, Via or Vib
Input differential threshold
Input differential hysteresis
Receiver differential input impedance
Maximum Clock Rate
Output voltage high, Voa or Vob
Output voltage low, Voa or Vob
Output differential voltage
Output offset voltage
Output impedance, single ended
Ro mismatch between A & B
Change in |Vod| between ‘0’ and ‘1’
Change in Vos between ‘0’ and ‘1’
Output current – Driver shorted to ground
Output current – Drivers shorted together
Power-off output leakage
Maximum Clock Rate
Differential peak-to-peak Voltage
Common Mode Voltage
Maximum Clock Rate
Maximum Clock Rate (SCLK, 1/t
SCLK
)
Minimum pulse width high, t
PWH
Minimum pulse width low, t
PWL
Minimum SDIO and CSB to SCLK setup, t
DS
Minimum SCLK to SDIO hold, t
DH
Maximum SCLK to valid SDIO and SDO, t
DV
Minimum SCLK to invalid SDIO and SDO, t
DNV
825
-100
80
1200
825
-100
80
600
1025
150
1150
80
600
1200
20
20
1575
100
120
1575
100
120
1375
250
1250
120
10
25
25
20
4
TBD
20
mV
mV
mV
MSPS
Err/Bit
mV
mV
mV
MHz
mV
mV
mV
mV
%
mV
mV
mA
mA
mA
MHz
mV
mV
MHz
MHz
ns
ns
ns
ns
ns
ns
20
TBD
20
200
100
800
400
10
5
20
5
LVDS DATA INPUTS (DB[13:0]+, DB[13:0]-)
DB+ = Via, DB- = Vib
LVDS CLOCK INPUT (DATACLK_IN+, DATACLK_IN-)
DATACLK+ = Via, DATACLK- = Vib
LVDS CLOCK OUTPUT (DATACLK_OUT+, DATACLK_ OUT-)
DATACLK_OUT+ = Voa, DATACLK_OUT- = Vob
100 ohm termination
DAC CLOCK INPUT (CLK+, CLK-)
SERIAL PERIPHERAL INTERFACE
Table 2: Digital Specifications
1
LVDS Drivers and Receivers are compliant to the IEEE-1596 Reduced Range Link, unless otherwise noted
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