參數(shù)資料
型號： AD9734
廠商： Analog Devices, Inc.
英文描述： 14/12/10-Bit, 1200 MSPS D/A Converters
中文描述： 14/12/10-Bit，1200 MSPS的D / A轉換
文件頁數(shù)： 22/42頁
文件大?。?/td> 934K
代理商： AD9734
AD9736/AD9735/AD9734
Preliminary Technical Data
AD9736 DATA INTERFACE CONTROLLERS
Rev. PrJ | Page 22 of 42
There are 2 internal controllers that can be utilized in the operation
of the AD9736. The first controller helps maintain optimum LVDS
data sampling and the second controller helps maintain optimum
synchronization between the DACCLK and the incoming data. The
LVDS controller is responsible for optimizing the sampling of the
data from the LVDS bus (DB13:0) while the SYNC controller
resolves timing problems between the DAC_CLK (CLK+, CLK-)
and the DATACLK. A block diagram of these controllers is shown
in Figure 23.
The controllers are clocked with a divided down version of the
DAC_CLK. The divide ratio is set utilizing the controller clock
predivider bits (CCD<3:0>) located at REG22 bits 3:0 to generate
the controller clock as follows:
Controller Clock = DAC_CLK / ( 2 ^ ( CCD<3 :0> + 4 ))
NOTE
: The controller clock may not exceed 10MHz for correct
operation. Until CCD<3:0> has been properly programmed to
meet this requirement the DAC output may not be stable.
The LVDS and SYNC controllers can be independently operated in
3 different modes via SPI port REG06 and REG08.
1.
2.
3.
Manual Mode
Surveillance Mode
Auto Mode
In manual mode all of the timing measurements and updates are
externally controlled via the SPI.
In surveillance mode each controller takes measurements and
calculates a new “optimal” value continuously. The result of the
measurement can be passed through an averaging filter before
evaluating the results for increased noise immunity. The filtered
result is compared to a threshold value set via REG06 and REG08
of the SPI port. If the error is greater then the threshold, an
interrupt is triggered and the controller stops. REG01 of the SPI
port controls the interrupts with bits 3 and 2 enabling the
respective interrupts and bits 7 and 6 indicating the respective
controller’s interrupt. If an interrupt is enabled it will also activate
the AD9736’s IRQ pin. In order to clear an interrupt the interrupt
enable bit of the respective controller must be set to a zero for at
least one controller clock cycle (controller clock < 10MHz).
Auto mode is almost identical to surveillance mode. Instead of
triggering an interrupt and stopping the controller, the controller
automatically updates its settings to the newly calculated “optimal”
value and continues to run.
Figure 23.AD9736 Internal Synchronization Engine
i.e. FPGA
LOGIC
FIFO
LOGIC
DAC
DACCLK
DATACLK_OUT
DB<13:0>
DATACLK_IN
CLK Control
Controller
Controller
Data Source
LVDS
SAMPLE
SYNC
LVDS
SYNC
相關PDF資料
PDF描述
AD9735 14/12/10-Bit, 1200 MSPS D/A Converters
AD9736 14/12/10-Bit, 1200 MSPS D/A Converters
AD9736-EB 14/12/10-Bit, 1200 MSPS D/A Converters
AD9736BBC 14/12/10-Bit, 1200 MSPS D/A Converters
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相關代理商/技術參數(shù)
參數(shù)描述
AD9734_06 制造商:AD 制造商全稱:Analog Devices 功能描述:10-/12-/14-Bit, 1200 MSPS DACS
AD9734BBC 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD9734BBCRL 制造商:Analog Devices 功能描述:DAC SGL 10-BIT 160CSPBGA - Tape and Reel
AD9734BBCZ 功能描述:IC DAC 10BIT 1.2GSPS 160-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 標準包裝:1 系列:- 設置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND
AD9734BBCZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:10-/12-/14-Bit, 1200 MSPS DACS
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