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參數(shù)資料
| 型號(hào)： | AD9734 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14/12/10-Bit, 1200 MSPS D/A Converters |
| 中文描述： | 14/12/10-Bit，1200 MSPS的D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 26/42頁 |
| 文件大?。?/td> | 934K |
| 代理商： | AD9734 |
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AD9736/AD9735/AD9734
Preliminary Technical Data
Rev. PrJ | Page 26 of 42
OPERATION IN SURVEILLANCE AND AUTO MODES
Once FIFOSTAT<2:0> has been manually placed in an optimal
state the AD9736 SYNC logic can be run in Surveillance or Auto
mode. To start, turn on Surveillance mode by setting SSURV = 1
(REG08, bit 7) then enable the sync interrupt (REG01, bit 2). If
STRH<0> = 0 (REG08, bit 0) an interrupt will occur if
FIFOSTAT<2:0> = 0 or 7. If STRH<0> = 1 (REG08, bit 0) an
interrupt will occur if FIFOSTAT<2:0> = 0, 1, 6 or 7. The interrupt
can be read at REG01, bit 6 at the AD9736 IRQ pin.
To enter Auto mode, complete the preceding steps then set SAUTO
= 1 (REG09, bit 6). Next set the SYNC interrupt = 0 (REG01, bit 2),
to allow the phase offset (PHOF<1:0>) to be automatically updated
if FIFOSTAT<2:0> violates the threshold value.
The FIFOSTAT signal is filtered to improve noise immunity and
reduce unnecessary phase offset updates. The filter operates with
the following algorithm:
FIFOSTAT = FIFOSTAT + Delta FIFOSTAT / 2 ^ SFLT<3:0>
Where 0 <= SFLT<3:0> <= 12. Values greater than 12 are set to 12.
SAMPLE_HOLD
SAMPLE_SETUP
SAMPLE_DELAY
EXTERNAL_DELAY
INTERNAL_DELAY
B
C
D
E
F
G
H
I
J
K
M
O
L
N
P
R
Q
A
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
0
1
2
3
4
5
6
7
0
1
2
3
A
C
E
G
I
K
M
4
5
6
7
0
1
2
3
4
5
6
7
4
0
4
4
4
A
B
C
D
E
F
G
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M
5
6
7
0
1
B
D
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1
2
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4
DACCLK
DATACLK_OUT
DATACLK_IN
DATA_IN
CSS1
D1
CSS2
D2
WRITE_PTR1
M0
M1
M2
M3
M4
M5
M6
M7
READ_PTR1
FIFOSTAT
DAC_DATA
Figure 29. SYNC Logic Timing Diagram
Safe Zone
Error Zone
Data ‘A’ can be
safely read from
the FIFO in the
Safe Zone. In
the Error Zone,
the pointers
may briefly
overlap due to
clock jitter or
FIFOSTAT is set
equal to the
write pointer
each time the
read pointer
changes from 7
to 0.
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| AD9734BBCZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-/12-/14-Bit, 1200 MSPS DACS |
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