參數(shù)資料
型號(hào)： AD9734
廠商： Analog Devices, Inc.
英文描述： 14/12/10-Bit, 1200 MSPS D/A Converters
中文描述： 14/12/10-Bit，1200 MSPS的D / A轉(zhuǎn)換
文件頁(yè)數(shù)： 16/42頁(yè)
文件大?。?/td> 934K
代理商： AD9734
AD9736/AD9735/AD9734
Preliminary Technical Data
Rev. PrJ | Page 16 of 42
REG 02, 03 -> Full Scale Current (FSC)
Reading REG 02 & 03 return previously written values for all defined register bits unless otherwise noted. Reset value in
bold
text.
ADR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x02
FSC_1
SLEEP
FSC<9>
FSC<8>
0x03
FSC_2
FSC<7>
FSC<6>
FSC<5>
FSC<4>
FSC<3>
FSC<2>
FSC<1>
FSC<0>
SLEEP
: WRITE ->
0
, Enable DAC output
1, Set DAC output current to 0mA
FSC<9:0>
: WRITE ->
0x000, 10mA full scale output current
0x200
, 20mA full scale output current
0x3FF, 30mA full scale output current
NOTE: Iout = (72 + 192 * ( FSC<9:0> / 1024 ) ) * I120
where I120 = Vref / R120u, for example 1.2V / 10k = 120uA
REG 04, 05, 06 -> LVDS Controller (LVDS_CNT)
Reading REG 04, 05 & 06 return previously written values for all defined register bits unless otherwise noted. Reset value in
bold
text.
ADR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x04
LVDS_CNT1
MSD<3>
MSD<2>
MSD<1>
MSD<0>
MHD<3>
MHD<2>
MHD<1>
MHD<0>
0x05
LVDS_CNT2
SD<3>
SD<2>
SD<1>
SD<0>
LCHANGE
ERR_HI
ERR_LO
CHECK
0x06
LVDS_CNT3
LSURV
LAUTO
LFLT<3>
LFLT<2>
LFLT<1>
LFLT<0>
LTRH<1>
LTRH<0>
MSD<3:0>
: WRITE ->
0x0
, Set setup delay for the measurement system
: READ ->
If ( LAUTO == 1) the latest measured value for the setup delay
If ( LAUTO == 0) read back of the last SPI write to this bit
MHD<3:0>
: WRITE ->
0x0
, Set hold delay for the measurement system
: READ ->
If ( LAUTO == 1) the latest measured value for the hold delay
If ( LAUTO == 0) read back of the last SPI write to this bit
SD<3:0>
: WRITE->
0x0
, Set sample delay
: READ ->
If ( LAUTO == 1) the result of a measurement cycle is stored in this register
If ( LAUTO == 0) read back of the last SPI write to this bit
LCHANGE
: READ ->
0, No change from previous measurement
1, Change in value from the previous measurement
NOTE: The average filter and the threshold detection are not applied to this bit
ERR_HI
: READ ->
One of the 15 LVDS inputs is above the input voltage limits of the IEEE reduce link spec.
ERR_LO
: READ ->
One of the 15 LVDS inputs is below the input voltage limits of the IEEE reduced link spec.
CHECK
: READ ->
0, Phase measurement – sampling in the previous or following DATA cycle
1, Phase measurement – sampling in the correct DATA cycle
LSURV
: WRITE ->
0
, The controller stops after completion of the current measurement cycle
1, Continuous measurements are taken and an interrupt is issued if the clock alignment drifts beyond the threshold value
LAUTO
: WRITE ->
0
, Sample delay is not automatically updated
1, Continuously starts measurement cycles and updates the sample delay according to the measurement
NOTE: LSURV (REG06 Bit 7) must be set to 1 and the LVDS IRQ (REG01 Bit 3) must be set to 0 for AUTO mode
LFLT<3:0>
: WRITE ->
0x0
, Average filter length, Delay = Delay + Delta Delay / 2^ LFLT<3:0>, values greater than 12 (0x0C) are clipped to 12
相關(guān)PDF資料
PDF描述
AD9735 14/12/10-Bit, 1200 MSPS D/A Converters
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AD9736BBC 14/12/10-Bit, 1200 MSPS D/A Converters
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