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參數(shù)資料
| 型號： | AD9734 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14/12/10-Bit, 1200 MSPS D/A Converters |
| 中文描述： | 14/12/10-Bit，1200 MSPS的D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 23/42頁 |
| 文件大?。?/td> | 934K |
| 代理商： | AD9734 |
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Preliminary Technical Data
AD9736/AD9735/AD9734
AD9736 LVDS Sample Logic
Rev. PrJ | Page 23 of 42
A simplified
diagram of the AD9736 LVDS data sampling engine is
shown in Figure 24, with the timing relationships shown in Figure
25.
The incoming LVDS data is latched by the DATA SAMPLING
SIGNAL (DSS) which is derived from DATACLK_IN. The LVDS
controller delays DATACLK_IN to create the DATA SAMPLING
SIGNAL (DSS) which is adjusted to sample the LVDS data in the
center of the valid data window. The skew between the
DATACLK_IN and the LVDS data bits (DB<13:0>) must be
minimal (t1 and t2 in Figure 25) for proper operation. Therefore, it
is recommended that the DATACLK_IN be generated in the same
manner as the LVDS data bits (DB<13:0>) with the same driver and
data lines (i.e. it should just be another LVDS data bit running a
constant 01010101… sequence, as shown in Figure 35).
Figure 24. AD9736 Internal LVDS Data Sampling Logic
LVDS SAMPLE LOGIC CALIBRATION
The internal DATA SAMPLING SIGNAL delay must be calibrated
to optimize the data sample timing. Once calibrated, the AD9736
can generate an IRQ or automatically correct its timing if
temperature or voltage variations change the timing too much. This
calibration is done by using the delayed CLOCK SAMPLING
SIGNAL (CSS) to sample the DELAYED CLOCK SIGNAL (DCS).
The LVDS sampling logic can find the edges of the DATACLK_IN
signal and from this measurement the center of the valid data
window can be located.
The internal delay line which derives the delayed DATA
SAMPLING SIGNAL (DSS) from DATACLK_IN is controlled by
SD3:0 (REG05, bits 7:4) while the DELAYED CLOCK SIGNAL
(DCS) is controlled by MSD3:0 (REG04, bits 7:4) and the CLOCK
SAMPLING SIGNAL (CSS) is controlled by MHD3:0 (REG04, bits
3:0).
DATACLK_IN transitions must be time aligned with the LVDS
data (DB<13:0>) transitions. This allows the CLOCK SAMPLING
SIGNAL (CSS, derived from the DATACLK_IN), to find the valid
data window of DB<13:0> by locating the DATACLK_IN edges.
The latching (rising) edge of CSS is initially placed using bits
SD<3:0> and can then be shifted to the left using MSD<3:0> and to
the right using MHD<3:0>. When CSS samples the DELAYED
CLOCK SIGNAL (DCS) and the result is a 1, (which can be read
back via the CHECK bit at REG05, bit 0) then the sampling is
occurring in the correct data cycle. In order to find the leading
edge of the data cycle, increment MSD (Measured Set-up Delay)
until CHECK goes low. In order to find the trailing edge, increment
MHD (Measured Hold Delay) until CHECK goes low. Always set
MHD = 0 when incrementing MSD and vice-versa.
Note:
The incremental units of SD, MSD, and MHD are in units of
real time, not fractions of a clock cycle. At this time, the delay from
each increment of these bits has not been fully characterized. Over
process, voltage, and temperature, each increment may introduce
between 25 and 100ps of delay with a nominal target of 80ps.
OPERATING THE LVDS CONTROLLER IN MANUAL
MODE VIA THE SPI PORT
The manual operation of the LVDS controller allows the user to
step through both the set-up and hold delays to calculate the
optimal sampling delay (i.e. center of the data eye).
With SD<3:0> and MHD<3:0> set to zero, increment the set-up
time delay (MSD<3:0>, REG04, bits 7:4) until the check bit
(REG05, bit 0) goes low and record this value. This locates the
leading DATACLK_IN (and DATA) transition as shown in Figure
26.
With SD<3:0> and MSD<3:0> set to zero, increment the hold time
delay (MHD<3:0>, REG04, bits 3:0) until the check bit (REG05 bit
0) goes low and record this value. This locates the trailing
DATACLK_IN (and DATA) transition as shown in Figure 27.
Once both DATACLK_IN edges are located the Sample Delay
(SD<3:0>, REG05, bits 7:4) must be updated according to the
following equation:
Sample Delay = ( MHD – MSD ) / 2
After updating SD<3:0>, verify that the sampling signal is in the
middle of the valid data window by adjusting both MHD then
MSD with the new sample delay until the CHECK bit goes low. The
new MHD and MSD values should be equal or within one unit
delay if SD<3:0> was set correctly.
NOTE
: The Sample Delay calibration just described should be
performed prior to enabling Surveillance mode or Auto mode.
LVDS
RX
LVDS
RX
FF
SD<3:0>
Sample Delay
FF
D1
D2
DB<13:0>
DATACLK
IN
DATA SAMPLING
SIGNAL
FF
MSD<3:0>
Delay
MHD<3:0>
Delay
CHECK
CLOCK
SAMPLING
SIGNAL
DELAYED
CLOCK
SIGNAL
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| AD9736BBC | 14/12/10-Bit, 1200 MSPS D/A Converters |
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