參數(shù)資料
型號(hào)： AD9734
廠商： Analog Devices, Inc.
英文描述： 14/12/10-Bit, 1200 MSPS D/A Converters
中文描述： 14/12/10-Bit，1200 MSPS的D / A轉(zhuǎn)換
文件頁(yè)數(shù)： 18/42頁(yè)
文件大?。?/td> 934K
代理商： AD9734
AD9736/AD9735/AD9734
Preliminary Technical Data
Rev. PrJ | Page 18 of 42
REG 17, 18, 19, 20, 21 -> Built-in Self Test Control (BIST_CNT)
Reading REG17, 18, 19, 20 & 21 return previously written values for all defined register bits unless otherwise noted. Reset value in
bold
text.
ADR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x11
BIST_CNT
SEL<1>
SEL<0>
SIG_READ
LVDS_EN
SYNC_EN
CLEAR
0x12
BIST<7:0>
BIST<7>
BIST<6>
BIST<5>
BIST<4>
BIST<3>
BIST<2>
BIST<1>
BIST<0>
0x13
BIST<15:8>
BIST<15>
BIST<14>
BIST<13>
BIST<12>
BIST<11>
BIST<10>
BIST<9>
BIST<8>
0x14
BIST<23:16>
BIST<23>
BIST<22>
BIST<21>
BIST<20>
BIST<19>
BIST<18>
BIST<17>
BIST<16>
0x15
BIST<31:24>
BIST<31>
BIST<30>
BIST<29>
BIST<28>
BIST<27>
BIST<26>
BIST<25>
BIST<24>
SEL<1:0>
: WRITE ->
00, Write result of the LVDS Phase 1 BIST to BIST<31:0>
01, Write result of the LVDS Phase 2 BIST to BIST<31:0>
10, Write result of the SYNC Phase 1 BIST to BIST<31:0>
11, Write result of the SYNC Phase 2 BIST to BIST<31:0>
SIG_READ
: WRITE ->
0, No action
1, Enable BIST signature readback
LVDS_EN
: WRITE->
0, No action
1, Enable LVDS BIST
SYNC_EN
: WRITE ->
0, No Action
1, Enable SYNC BIST
CLEAR
: WRITE ->
0, No Action
1, Clear all BIST registers
BIST<31:0>
: READ ->
Results of the Built-in Self Test
REG 22 -> Controller Clock Pre-divider (CCLK_DIV)
Reading REG 22 returns previously written values for all defined register bits unless otherwise noted. Reset value in
bold
text.
ADR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x16
CCLK_DIV
RESV’D
RESV’D
RESV’D
RESV’D
CCD<3>
CCD<2>
CCD<1>
CCD<0>
CCD<3:0>
: WRITE ->
0x0
, Controller Clock = DACCLK / 16
0x1, Controller Clock = DACCLK / 32
0x2, Controller Clock = DACCLK / 64 …
0xF, Controller Clock = DACCLK / 524288
NOTE: The 100MHz to 1.2GHz DACCLK must be divided to less than 10MHz for correct operation. CCD<3:0> must be programmed to
divide the DACCLK so that this relationship is not violated. Controller Clock = DACCLK / ( 2 ^ ( CCD<3:0> + 4 ))
REG 31 -> VERSION
Reading REG 31 returns previously written values for all defined register bits unless otherwise noted. Reset value in
bold
text.
ADR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x1F
VERSION
VER<5>
VER<4>
VER<3>
VER<2>
VER<1>
VER<0>
RES10
RES12
VER<5:0>
: READ ->
Version number (part ID), 00001, Revision 1, initial release
RES10 (msb)
RES12 (lsb)
: READ ->
00, 14-bit DAC
01, 12-bit DAC
10, 10-bit DAC
相關(guān)PDF資料
PDF描述
AD9735 14/12/10-Bit, 1200 MSPS D/A Converters
AD9736 14/12/10-Bit, 1200 MSPS D/A Converters
AD9736-EB 14/12/10-Bit, 1200 MSPS D/A Converters
AD9736BBC 14/12/10-Bit, 1200 MSPS D/A Converters
AD974(中文) 4-Channel, 16-Bit, 200 kSPS Data Acquisition System(4通道,200kSPS16位數(shù)據(jù)采集系統(tǒng))
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9734_06 制造商:AD 制造商全稱:Analog Devices 功能描述:10-/12-/14-Bit, 1200 MSPS DACS
AD9734BBC 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD9734BBCRL 制造商:Analog Devices 功能描述:DAC SGL 10-BIT 160CSPBGA - Tape and Reel
AD9734BBCZ 功能描述:IC DAC 10BIT 1.2GSPS 160-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND
AD9734BBCZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:10-/12-/14-Bit, 1200 MSPS DACS
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