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參數(shù)資料
| 型號： | AD9734 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14/12/10-Bit, 1200 MSPS D/A Converters |
| 中文描述： | 14/12/10-Bit，1200 MSPS的D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 19/42頁 |
| 文件大小： | 934K |
| 代理商： | AD9734 |
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Preliminary Technical Data
AD9736/AD9735/AD9734
GENERAL DESCRIPTION
Rev. PrJ | Page 19 of 42
The AD9736/35/34 are 14/12/10-bit DACs which run at an update
rate up to 1.2GSPS. Input data can be accepted up to the full
1.2GSPS rate or a 2x interpolation filter may be enabled (2x mode)
allowing full-speed operation with a 600MSPS input data rate.
DATA and DATACLK_IN inputs are parallel LVDS meeting the
IEEE reduced swing LVDS specifications with the exception of
input hysteresis. The DATACLK_IN input runs at one half the
input DATA rate in a double data rate (DDR) format. Each edge of
DATACLK_IN is used to transfer DATA into the AD9736 as shown
in Figure 25.
The DACCLK (pins E1, F1) directly drives the DAC core to
minimize clock jitter. It is also divided by two (1x and 2x mode)
then output as the DATACLK_OUT. The DATACLK_OUT signal
is used to clock the data source. The DAC expects DDR LVDS data
(DB<13:0>) aligned with the DDR input clock (DATACLK_IN)
from a circuit similar to the one shown in Figure 35. Clock
relationships are shown in Table 6.
MODE
DACCLK
DATACLK
OUT
600MHz
600MHz
DATACLK
IN
600MHz
300MHz
DATA
1x
2x
1.2GHz
1.2GHz
1.2GSPS
600MSPS
Table 6. AD9736 Clock Relationships
Maintaining correct alignment of data and clock is a common
challenge with high-speed DACs, complicated by changes in
temperature and other operating conditions. The AD9736
simplifies this high-speed data capture problem with two adaptive
closed-loop timing controllers.
One timing controller manages the LVDS data and data clock
alignment (LVDS controller) and the other manages the LVDS data
and DACCLK alignment (SYNC controller). The LVDS controller
locates the data transitions and delays the DATACLK_IN so that its
transition is in the center of the valid data window. The SYNC
controller manages the FIFO that moves data from the LVDS
DATACLK_IN domain to the DACCLK domain. Both controllers
can be operated in manual mode under external processor control,
surveillance mode where error conditions generate external
interrupts or automatic mode where errors are automatically
corrected.
The LVDS and SYNC controllers include moving average filtering
for noise immunity and variable thresholds to control their activity.
Normally the controllers can be set to run in automatic mode and
they will make any necessary adjustments without dropping or
duplicating samples sent to the DAC. Both controllers require
initial calibration prior to entering automatic update mode.
Control of the AD9736 functions is via the serially programmed
registers listed in Table 5.
Serial Peripheral Interface
The AD9736 serial port is a flexible, synchronous serial
communications port allowing easy interface to many industry-
standard microcontrollers and microprocessors. The serial I/O is
compatible with most synchronous transfer formats, including both
the Motorola SPI and Intel SSR protocols. The interface allows
read/write access to all registers that configure the AD9736. Single
or multiple byte transfers are supported, as well as MSB first or LSB
first transfer formats. The AD9736’s serial interface port can be
configured as a single pin I/O (SDIO) or two unidirectional pins for
in/out (SDIO/SDO).
Figure 18. AD9736 SPI Port
The AD9736 may optionally be configured via external pins rather
than the serial interface. When the PIN_MODE input (pin L1) is
high the serial interface is disabled and its pins are reassigned for
direct control of the DAC. Specific functionality is described in the
PIN Mode section.
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communication cycle with the AD9736.
Phase 1 is the instruction cycle, which is the writing of an
instruction byte into the AD9736, coincident with the first eight
SCLK rising edges. The instruction byte provides the AD9736 serial
port controller with information regarding the data transfer cycle,
which is Phase 2 of the communication cycle. The Phase 1
instruction byte defines whether the upcoming data transfer is read
or write, the number of bytes in the data transfer, and the starting
register address for the first byte of the data transfer. The first eight
SCLK rising edges of each communication cycle are used to write
the instruction byte into the AD9736.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9736 and
the system controller. Phase 2 of the communication cycle is a
transfer of 1, 2, 3, or 4 data bytes as determined by the instruction
byte. Using one multibyte transfer is the preferred method. Single
byte data transfers are useful to reduce CPU overhead when
register access requires one byte only. Registers change immediately
upon writing to the last bit of each transfer byte.
CSB can be raised after each sequence of 8 bits (except the last byte)
to stall the bus. The serial transfer will resume when CSB is
lowered. Stalling on non-byte boundaries will reset the SPI.
SDO (Pin G14)
SDIO (Pin F14)
SCLK (Pin G13)
CSB (Pin F13)
AD9736
SPI Port
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