參數(shù)資料
型號(hào)： AD9557BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 72/92頁(yè)
文件大小： 0K
描述： IC CLOCK TRANSLATOR 40LFCSP
產(chǎn)品變化通告： Minor Mask Change 11/Apr/2012
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/頻率轉(zhuǎn)換器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，HSTL，LVDS
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.25GHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 托盤
AD9557
Data Sheet
Rev. B | Page 74 of 92
OUTPUT CLOCK DISTRIBUTION (REGISTER 0x0500 TO REGISTER 0x0515)
Table 67. Distribution Output Synchronization Settings
Address
Bits
Bit Name
Description
0x0500
[7:6]
Reserved
Reserved.
5
Mask Channel 1 sync
Masks the synchronous reset to the Channel 1 divider.
0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs.
1 = masked. Setting this bit asynchronously releases Channel 1 from the static sync state,
thus allowing the Channel 1 divider to toggle. Channel 1 ignores all sync events while this
bit is set. Setting this bit does not enable the output drivers connected to this channel.
In addition, the output distribution sync also depends on the setting of Register 0x0405[3].
4
Mask Channel 0 sync
Masks the synchronous reset to the Channel 0 divider.
0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs.
1 = masked. Setting this bit asynchronously releases Channel 0 from the static sync state,
thus allowing the Channel 0 divider to toggle. Channel 0 ignores all sync events while this
bit is set. Setting this bit does not enable the output drivers connected to this channel.
In addition, the output distribution sync also depends on the setting of Register 0x0405[3].
3
Reserved
Reserved.
2
Sync source selection
Selects the sync source for the clock distribution output channels.
0 (default) = direct. The sync pulse occurs on the next I/O update.
1 = active reference.
Note that the output distribution sync also depends on the APLL being calibrated and
locked, unless Register 0x0405[3] = 1b.
[1:0]
Automatic sync mode
Autosync mode.
00 = disabled. A sync command must be issued manually or by using the sync mask bits
in this register (Bits[5:4]).
01 = sync on DPLL frequency lock.
10 (default) = sync on DPLL phase lock.
11 = reserved.
Table 68. Distribution OUT0 Setting
Address
Bits
Bit Name
Description
0x0501
7
Enable 3.3 V CMOS driver
0 (default) = disables 3.3 V CMOS driver, and OUT0 logic is controlled by Register 0x0501[6:4]
1 = enables 3.3 V CMOS driver as operating mode of OUT0.
This bit should be set to 1b only if Bits[6:4] are in CMOS mode.
[6:4]
OUT0 format
These bits set the OUT0 driver mode.
000 = PD, tristate.
001 (default) = HSTL.
010 = LVDS.
011 = reserved.
100 = CMOS, both outputs active.
101 = CMOS, P output active, N output power-down.
110 = CMOS, N output active, P output power-down.
111 = reserved.
[3:2]
OUT0 polarity
Controls the OUT0 polarity.
00 (default) = positive, negative.
01 = positive, positive.
10 = negative, positive.
11 = negative, nevative.
1
OUT0 drive strength
Controls the output drive capability of OUT0.
0 (default) = CMOS: low drive strength; LVDS: 3.5 mA nominal.
1 = CMOS: normal drive strength; LVDS: 4.5 mA nominal (LVDS boost mode).
Note that this is only in 3.3 V CMOS mode for CMOS strength. 1.8 V CMOS has only the
low drive strength.
0
Enable OUT0
Enables/disables (1b/0b) OUT0 1.8 V driver (default is disabled).
This bit does not enable/disable OUT0 if Bit 7 of this register is set to 1.
相關(guān)PDF資料
PDF描述
V375C36M150BG CONVERTER MOD DC/DC 36V 150W
AD9547BCPZ IC CLOCK GEN/SYNCHRONIZR 64LFCSP
D38999/20MF11JN CONN RCPT 11POS WALL MNT W/SCKT
AD9549ABCPZ IC CLOCK GEN/SYNCHRONIZR 64LFCSP
ADN2814ACPZ IC CLOCK/DATA RECOVERY 32LFCSP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9557BCPZ-REEL7 功能描述:IC CLK XLATR PLL 1250MHZ 40LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件
AD9558 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad Input Multiservice Line Card Adaptive
AD9558/PCBZ 功能描述:BOARD EVAL FOR AD9558 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081
AD9558BCPZ 功能描述:IC CLOCK TRANSLATOR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6
AD9558BCPZ-REEL7 功能描述:IC CLK XLATR PLL 1250MHZ 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*