參數(shù)資料
型號： AD9557BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 39/92頁
文件大?。?/td> 0K
描述： IC CLOCK TRANSLATOR 40LFCSP
產(chǎn)品變化通告： Minor Mask Change 11/Apr/2012
標準包裝： 1
類型： 時鐘/頻率轉(zhuǎn)換器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，HSTL，LVDS
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.25GHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 托盤
AD9557
Data Sheet
Rev. B | Page 44 of 92
SERIAL CONTROL PORT
The AD9557 serial control port is a flexible, synchronous serial
communications port that provides a convenient interface to
many industry-standard microcontrollers and microprocessors.
The serial control port is compatible with most synchronous
transfer formats, including IC, Motorola SPI, and Intel SSR
protocols. The serial control port allows read/write access to the
AD9557 register map.
In SPI mode, single or multiple byte transfers are supported.
The SPI port configuration is programmable via Register 0x0000.
This register is integrated into the SPI control logic rather than
in the register map and is distinct from the I2C Register 0x0000.
It is also inaccessible to the EEPROM controller.
Although the AD9557 supports both the SPI and I2C serial port
protocols, only one or the other is active following power-up
(as determined by the M0 and M1 multifunction pins during
the startup sequence). That is, the only way to change the serial
port protocol is to reset the device (or cycle the device power
supply).
SPI/IC PORT SELECTION
Because the AD9557 supports both SPI and IC protocols, the
active serial port protocol depends on the logic state of the
PINCONTROL, M1, and M0 pins. The PINCONTROL pin
must be low, and the state of the M0 and M1 pins determines
the I2C address, or if SPI mode is enabled. See Table 24 for the
I2C address assignments.
Table 24. SPI/IC Serial Port Setup
M1
M0
SPI/IC
Low
SPI
Low
Open
IC, 1101000
Low
High
IC, 1101001
Open
Low
IC, 1101010
Open
IC, 1101011
Open
High
IC, 1101100
High
Low
IC, 1101101
High
Open
IC, 1101110
High
IC, 1101111
SPI SERIAL PORT OPERATION
Pin Descriptions
The SCLK (serial clock) pin serves as the serial shift clock. This
pin is an input. SCLK synchronizes serial control port read and
write operations. The rising edge SCLK registers write data bits,
and the falling edge registers read data bits. The SCLK pin
supports a maximum clock rate of 40 MHz.
The SDIO (serial data input/output) pin is a dual-purpose pin
and acts as either an input only (unidirectional mode) or as both
an input and an output (bidirectional mode). The AD9557
default SPI mode is bidirectional.
The SDO (serial data output) pin is useful only in unidirectional
I/O mode. It serves as the data output pin for read operations.
The
EE
AA
(chip select) pin is an active low control that gates read
and write operations. This pin is internally connected to a 30 k
pull-up resistor. When
AA
CSEE
AA
is high, the SDO and SDIO pins go
into a high impedance state.
CS
SPI Mode Operation
The SPI port supports both 3-wire (bidirectional) and 4-wire
(unidirectional) hardware configurations and both MSB-first
and LSB-first data formats. Both the hardware configuration
and data format features are programmable. By default, the
AD9557 uses the bidirectional MSB-first mode. The reason that
bidirectional is the default mode is so that the user can still
write to the device, if it is wired for unidirectional operation, to
switch to unidirectional mode.
Assertion (active low) of the
AA
CSEE
AA
pin initiates a write or read
operation to the AD9557 SPI port. For data transfers of three
bytes or fewer (excluding the instruction word), the device
supports the
AA
CSEE
AA
stalled high mode (see Table 25). In this mode,
the
AA
CSEE
AA
pin can be temporarily deasserted on any byte boundary,
allowing time for the system controller to process the next byte.
AA
CSEE
AA
can be deasserted only on byte boundaries, however. This
applies to both the instruction and data portions of the transfer.
During stall high periods, the serial control port state machine
enters a wait state until all data is sent. If the system controller
decides to abort a transfer midstream, the state machine must be
reset either by completing the transfer or by asserting the
AA
CSEE
AA
pin for at least one complete SCLK cycle (but less than eight
SCLK cycles). Deasserting the
AA
CSEE
AA
pin on a nonbyte boundary
terminates the serial transfer and flushes the buffer.
In streaming mode (see Table 25), any number of data bytes can
be transferred in a continuous stream. The register address is
automatically incremented or decremented.
AA
CSEE
AA
must be deasserted
at the end of the last byte that is transferred, thereby ending the
stream mode.
Table 25. Byte Transfer Count
W1
W0
Bytes to Transfer
0
1
0
1
2
1
0
3
1
Streaming mode
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