I2C SERIAL PORT OPERATION
參數(shù)資料
型號(hào)： AD9557BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 43/92頁(yè)
文件大小： 0K
描述： IC CLOCK TRANSLATOR 40LFCSP
產(chǎn)品變化通告： Minor Mask Change 11/Apr/2012
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/頻率轉(zhuǎn)換器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，HSTL，LVDS
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.25GHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 托盤
AD9557
Data Sheet
Rev. B | Page 48 of 92
I2C SERIAL PORT OPERATION
The I2C interface has the advantage of requiring only two control
pins and is a de facto standard throughout the I2C industry.
However, its disadvantage is programming speed, which is
400 kbps maximum. The AD9557 I2C port design is based on
the I2C fast mode standard; therefore, it supports both the 100 kHz
standard mode and 400 kHz fast mode. Fast mode imposes a glitch
tolerance requirement on the control signals. That is, the input
receivers ignore pulses of less than 50 ns duration.
The AD9557 I2C port consists of a serial data line (SDA) and
a serial clock line (SCL). In an I2C bus system, the AD9557 is
connected to the serial bus (data bus SDA and clock bus SCL)
as a slave device; that is, no clock is generated by the AD9557.
The AD9557 uses direct 16-bit memory addressing instead of
traditional 8-bit memory addressing.
The AD9557 allows up to seven unique slave devices to occupy
the I2C bus. These are accessed via a 7-bit slave address that is
transmitted as part of an I2C packet. Only the device that has a
matching slave address responds to subsequent I2C commands.
Table 24 lists the supported device slave addresses.
I2C Bus Characteristics
A summary of the various I2C protocols appears in Table 29.
Table 29. I2C Bus Abbreviation Definitions
Abbreviation
Definition
S
Start
Sr
Repeated start
P
Stop
A
Acknowledge
A
E
Nonacknowledge
A
WE
Write
R
Read
The transfer of data is shown in Figure 49. One clock pulse is
generated for each data bit transferred. The data on the SDA
line must be stable during the high period of the clock. The
high or low state of the data line can change only when the
clock signal on the SCL line is low.
DATA LINE
STABLE;
DATA VALID
CHANGE
OF DATA
ALLOWED
SDA
SCL
0
91
97-
035
Figure 49. Valid Bit Transfer
Start/stop functionality is shown in Figure 50. The start condition
is characterized by a high-to-low transition on the SDA line while
SCL is high. The start condition is always generated by the master
to initialize a data transfer. The stop condition is characterized
by a low-to-high transition on the SDA line while SCL is high.
The stop condition is always generated by the master to terminate
a data transfer. Every byte on the SDA line must be eight bits long.
Each byte must be followed by an acknowledge bit; bytes are sent
MSB first.
The acknowledge bit (A) is the ninth bit attached to any 8-bit
data byte. An acknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the
byte has been received. It is done by pulling the SDA line low
during the ninth clock pulse after each 8-bit data byte.
The nonacknowledge bit (
A
AE
A
) is the ninth bit attached to any 8-
bit data byte. A nonacknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the
byte has not been received. It is done by leaving the SDA line
high during the ninth clock pulse after each 8-bit data byte.
SDA
START CONDITION
STOP CONDITION
SCL
S
P
09
197-
036
Figure 50. Start and Stop Conditions
12
89
12
3TO 7
89
10
SDA
SCL
S
MSB
ACK FROM
SLAVE RECEIVER
ACK FROM
SLAVE RECEIVER
P
09197-
037
Figure 51. Acknowledge Bit
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