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參數(shù)資料
| 型號： | AD9557BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 47/92頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK TRANSLATOR 40LFCSP |
| 產品變化通告： | Minor Mask Change 11/Apr/2012 |
| 標準包裝： | 1 |
| 類型： | 時鐘/頻率轉換器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL，LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.25GHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 托盤 |
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Data Sheet
AD9557
Rev. B | Page 51 of 92
PROGRAMMING THE I/O REGISTERS
The register map spans an address range from 0x0000 through
0x0E3C. Each address provides access to 1 byte (eight bits)
of data. Each individual register is identified by its four-digit
hexadecimal address (for example, Register 0x0A10). In some
cases, a group of addresses collectively defines a register.
In general, when a group of registers defines a control parameter,
the LSB of the value resides in the D0 position of the register
with the lowest address. The bit weight increases right to left,
from the lowest register address to the highest register address.
Note that the EEPROM storage sequence registers (Address 0x0E10
to Address 0x0E3C) are an exception to the above convention (see
the EEPROM Instructions section).
BUFFERED/ACTIVE REGISTERS
There are two copies of most registers: buffered and active. The
value in the active registers is the one that is in use. The buffered
registers are the ones that take effect the next time the user
writes 0x01 to the I/O update register (Register 0x0005).
Buffering the registers allows the user to update a group of
registers (like the digital loop filter coefficients) at the same
time, which avoids the potential of unpredictable behavior in
the part. Registers with an L in the option column are live,
meaning that they take effect the moment the serial port
transfers that data byte.
AUTOCLEAR REGISTERS
An A in the option column of the register map identifies an
autoclear register. Typically, the active value for an autoclear
register takes effect following an I/O update. The bit is cleared
by the internal device logic upon completion of the prescribed
action.
REGISTER ACCESS RESTRICTIONS
Read and write access to the register map may be restricted
depending on the register in question, the source and direction
of access, and the current state of the device. Each register can
be classified into one or more access types. When more than
one type applies, the most restrictive condition is the one that
applies.
Whenever access is denied to a register, all attempts to read the
register return a 0 byte, and all attempts to write to the register
are ignored. Access to nonexistent registers is handled in the
same way as for a denied register.
Regular Access
Registers with regular access do not fall into any other category.
Both read and write access to registers of this type can be from
either the serial ports or the EEPROM controller. However, only
one of these sources can have access to a register at any given
time (access is mutually exclusive). When the EEPROM controller
is active, in either load or store mode, it has exclusive access to
these registers.
Read-Only Access
An R in the option column of the register map identifies read-
only registers. Access is available at all times, including when
the EEPROM controller is active. Note that read-only registers
(R) are inaccessible to the EEPROM, as well.
Exclusion from EEPROM Access
An E in the option column of the register map identifies a
register with contents that are inaccessible to the EEPROM.
That is, the contents of this type of register cannot be
transferred directly to the EEPROM or vice versa. Note that
read-only registers (R) are inaccessible to the EEPROM, as well.
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