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參數(shù)資料
| 型號： | AD9557BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK TRANSLATOR 40LFCSP |
| 產(chǎn)品變化通告： | Minor Mask Change 11/Apr/2012 |
| 標準包裝： | 1 |
| 類型： | 時鐘/頻率轉(zhuǎn)換器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL，LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.25GHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 托盤 |
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Data Sheet
AD9557
Rev. B | Page 31 of 92
Programmable Digital Loop Filter
The AD9557 loop filter is a third-order digital IIR filter that is
analogous to the third-order analog loop shown in Figure 37.
C3
C2
C1
R2
R3
091
97-
015
Figure 37. Third Order Analog Loop Filter
The AD9557 loop filter block features a simplified architecture
in which the user enters the desired loop characteristics directly
into the profile registers. This architecture makes the calculation
of individual coefficients unnecessary in most cases, while still
offering complete flexibility.
The AD9557 has two preset digital loop filters: high (88.5°) phase
margin and normal (70°) phase margin. The loop filter coefficients
are stored in Register 0x0317 to Register 0x0322 for high phase
margin and Register 0x0323 to Register 0x032E for normal phase
margin. The high phase margin loop filter is intended for
applications in which the closed-loop transfer function must
not have greater than 0.1 dB of peaking.
Bit 0 of Register 0x070E selects which filter is used for Profile A,
and Bit 0 of 0x074E selects the filter for Profile B.
The loop bandwidth for Profile A is set in Register 0x070F to
Register 0x0711, and the loop bandwidth for Profile B is set in
Register 0x074F to Register 0x0751.
The two preset conditions should cover all of the intended
applications for the AD9557. For special cases where these
conditions must be modified, the tools for calculating these
coefficients are available by contacting Analog Devices directly.
DPLL Digitally Controlled Oscillator Free Run Frequency
The AD9557 uses a Σ-Δ modulator (SDM) as a digitally controlled
oscillator (DCO). The DCO free run frequency can be calculated by
30
_
2
0
8
2
FTW
f
SYS
freerun
dco
where FTW0 is the value in Register 0x0300 to Register 0x0303,
section for information on calculating the system clock frequency.
Adaptive Clocking
The AD9557 can support adaptive clocking applications such as
asynchronous mapping and demapping. In these applications,
the output frequency can be dynamically adjusted by up to
±100 ppm from the nominal output frequency without manually
breaking the DPLL loop and reprogramming the part. This
function is supported for REFA only, not REFB.
The following registers are used in this function:
Register 0x0717 (DPLL N1 divider)
Register 0x0718 to Register 0x071A (DPLL FRAC1 divider)
Register 0x071B to Register 0x071D (DPLL MOD1 divider)
Writing to these registers requires an I/O update by writing
0x01 to Register 0x0005 before the new values take effect.
To make small adjustments to the output frequency, the user
can vary the FRAC1 and issue an I/O update. The advantage to
using only FRAC1 to adjust the output frequency is that the
DPLL does not briefly enter holdover. Therefore, the FRAC1 bit
can be updated as fast as the phase detector frequency of the DPLL.
Writing to the N1 and MOD1 dividers allows for larger changes
to the output frequency. When the AD9557 detects that the N1
or MOD1 values have changed, it automatically enters and exits
holdover for a brief instant without any disturbance in the output
frequency. This limits how quickly the output frequency can be
adapted.
It is important to realize that the amount of frequency adjustment
is limited to ±100 ppm before the output PLL (APLL) needs
a recalibration. Variations that are larger than ±100 ppm are
possible, but the ability of the AD9557 to maintain lock over
temperature extremes may be compromised.
It is also important to remember that the rate of change in
output frequency depends on the DPLL loop bandwidth.
DPLL Phase Lock Detector
The DPLL contains an all-digital phase lock detector. The user
controls the threshold sensitivity and hysteresis of the phase
detector via the profile registers.
The phase lock detector behaves in a manner analogous to water in
a tub (see Figure 38). The total capacity of the tub is 4096 units
with 2048 denoting empty, 0 denoting the 50% point, and
+2048 denoting full. The tub also has a safeguard to prevent
overflow. Furthermore, the tub has a low water mark at 1024
and a high water mark at +1024. To change the water level, the
user adds water with a fill bucket or removes water with a drain
bucket. The user specifies the size of the fill and drain buckets
via the 8-bit fill rate and drain rate values in the profile registers.
0
2048
–2048
1024
–1024
LOCK LEVEL
UNLOCK LEVEL
LOCKED
UNLOCKED
PREVIOUS
STATE
FILL
RATE
DRAIN
RATE
091
97-
01
7
Figure 38. Lock Detector Diagram
The water level in the tub is what the lock detector uses to deter-
mine the lock and unlock conditions. When the water level is
below the low water mark (1024), the detector indicates an
unlock condition. Conversely, whenever the water level is above the
high water mark (+1024), the detector indicates a lock condition.
When the water level is between the marks, the detector holds
its last condition. This concept appears graphically in Figure 38,
with an overlay of an example of the instantaneous water level
(vertical) vs. time (horizontal) and the resulting lock/unlock states.
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