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參數(shù)資料
| 型號： | AD9557BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK TRANSLATOR 40LFCSP |
| 產(chǎn)品變化通告： | Minor Mask Change 11/Apr/2012 |
| 標準包裝： | 1 |
| 類型： | 時鐘/頻率轉(zhuǎn)換器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL，LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.25GHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 托盤 |
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Data Sheet
AD9557
Rev. B | Page 25 of 92
GETTING STARTED
CHIP POWER MONITOR AND STARTUP
The AD9557 monitors the voltage on the power supplies at
power-up. When DVDD3 is greater than 2.35 V ± 0.1 V and
DVDD and AVDD are greater than 1.4 V ± 0.05 V, the device
generates a 20 ms reset pulse. The power-up reset pulse is internal
and independent of the
A
RESETE
A
pin. This internal power-up reset
sequence eliminates the need for the user to provide external power
supply sequencing. Within 45 ns after the leading edge of the
internal reset pulse, the M3 to M0 multifunction pins behave
as high impedance digital inputs and continue to do so until
programmed otherwise.
During a device reset (either via the power-up reset pulse or the
A
RESETE
A
pin), the multifunction pins (M3 to M0) behave as high
impedance inputs; but upon removal of the reset condition,
level-sensitive latches capture the logic pattern present on the
multifunction pins.
MULTIFUNCTION PINS AT RESET/POWER-UP
The AD9557 requires the user to supply the desired logic
state to the PINCONTROL pin, as well as the M3 to M0 pins.
If PINCONTROL is high, the part is in hard pin programming
mode. See the Pin Program Function Description section for
details on hard pin programming.
At startup, there are three choices for the M3 to M0 pins: pull-up,
pull-down, and floating. If the PINCONTROL pin is low, the
M3 to M0 pins determine the following configurations:
Following a reset, the M1 and M0 pins determine whether
the serial port interface behaves according to the SPI or I2C
protocol. Specifically, 0x00 selects the SPI interface, and any
other value selects the I2C port. The 3-level logic of M1 and
M0 allows the user to select eight possible I2C addresses (see
Table 24 for details).
The M3 and M2 pins select which of the eight possible
EEPROM profiles are loaded, or if the EEPROM loading is
bypassed. Leaving M3 and M2 floating at startup bypasses
the EEPROM loading, and the factory defaults are used
instead (see Table 22 for details).
DEVICE REGISTER PROGRAMMING USING
A REGISTER SETUP FILE
The evaluation software contains a programming wizard and
a convenient graphical user interface that assists the user in
determining the optimal configuration for the DPLL, APLL,
and SYSCLK based on the desired input and output frequencies.
It generates a register setup file with a .STP extension that is
easily readable using a text editor.
After using the evaluation software to create the setup file, use
the following sequence to program the AD9557 once:
1. Register 0x0A01 = 0x20 (set user free run mode).
2. Register 0x0A02 = 0x02 (hold outputs in static SYNC).
(Skip this step if using SYNC on DPLL phase lock or SYNC
on DPLL frequency lock. See Register 0x0500[1:0].)
3. Register 0x0405 = 0x20 (clear APLL VCO calibration).
4. Write the register values in the STP file from Address 0x0000
to Address 0x032E.
5. Register 0x0005 = 0x01 (update all registers).
6. Write the rest of the registers in the STP file, starting at
Address 0x0400.
7. Register 0x0405 = 0x21 (calibrate APLLon next I/O update).
8. Register 0x0403 = 0x07 (configure APLL).
9. Register 0x0400 = 0x81 (configure APLL).
10. Register 0x0005 = 0x01 (update all registers).
11. Register 0x0A01[5] = 0b (clear user free run mode).
12. Register 0x0005 = 0x01 (update all registers).
REGISTER PROGRAMMING OVERVIEW
This section provides an overview of the register blocks in the
AD9557, describing what they do and why they are important.
Registers Differing from Defaults for Optimal Performance
Ensure that the following registers are programmed to the listed
values for optimal performance:
Register 0x0405[7:4] = 0x2
Register 0x0403 = 0x07
Register 0x0400 = 0x81
If the silicon revision (Register 0x000A) equals 0x21 or higher,
the values listed here are already the default values.
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