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參數(shù)資料
| 型號： | AD9552BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLOCK GEN LP 32LFCSP |
| 設(shè)計資源： | Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152) |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 時鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | 時鐘，晶體 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 900MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
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Data Sheet
AD9552
Rev. E | Page 17 of 32
PART INITIALIZATION AND AUTOMATIC POWER-
ON RESET
The AD9552 has an internal power-on reset circuit. At power-up,
internal logic relies on the internal reference monitor to select
either the crystal oscillator or the reference input and then
initiates VCO calibration using whichever is found. If both are
present, the external reference path is chosen.
VCO calibration is required in order for the device to lock. If
the input reference signal is not present, VCO calibration waits
until a valid input reference is present. As soon as an input
reference signal is present, VCO calibration starts. The user
should wait at least 3 ms for the VCO calibration routine to
finish before programming the VCO control register (Register
0x0E) via serial communication.
If the user wishes to use the crystal oscillator input even if the
reference input is present, the user needs to set Bit 0 (use crystal
resonator) in Register 0x1D.
Any change to the preset frequency selection pins or the PLL
divide ratios requires the user to recalibrate the VCO.
OUTPUT/INPUT FREQUENCY RELATIONSHIP
The frequency at OUT1 and OUT2 is a function of the PLL
feedback divider values (N, FRAC, and MOD) and the output
divider values (P0 and P1). The equations that define the
frequency at OUT1 and OUT2 (fOUT1 and fOUT2, respectively)
are as follows.
+
×
=
1
0
1
P
N
K
f
MOD
FRAC
REF
OUT
fOUT2 = fOUT1
where:
fREF is the input reference or crystal resonator frequency.
K is the input mode scale factor.
N is the integer feedback divider value.
FRAC and MOD are the fractional feedback divider values.
P0 and P1 are the OUT1 divider values.
The numerator of the fOUT1 equation contains the feedback division
factor, which has an integer part (N) due to an integer divider
along with an optional fractional part (FRAC/MOD) associated
with the feedback SDM.
The following constraints apply:
{
}
47
,
36
∈
MIN
N
{
}
255
,
1
,
+
∈
MIN
MIN N
N
{
}
575
,
048
,1
,
1
,
0
∈
FRAC
{
}
575
,
048
,1
,
2
,1
∈
MOD
{ }2
,
1
∈
K
{
}
11
,
5
,
4
0
∈
P
{
}
63
,
2
,
1
∈
P
Note that NMIN and K can each be one of two values. The value
of NMIN depends on the state of the SDM. NMIN = 36 when the
SDM is disabled or NMIN = 47 when it is enabled. The value of K
depends on the 2× frequency multiplier. K = 1 when the 2×
frequency multiplier is bypassed, or K = 2 when it is enabled.
The frequency at the input to the PFD (fPFD) is calculated as
follows:
fPFD = K × fREF
The operating range of the VCO (3.35 GHz ≤ fVCO ≤ 4.05 GHz)
places the following constraint on fPFD:
MHz
4050
MHz
3350
+
≤
+
MOD
FRAC
PFD
MOD
FRAC
N
f
N
CALCULATING DIVIDER VALUES
This section provides a three-step procedure for calculating the
divider values when given a specific fOUT1/fREF ratio (fREF is the
frequency of either the REF input signal source or the external
crystal resonator). The computation process is described in
general terms, but a specific example is provided for clarity.
The example is based on a frequency control pin setting of
A[2:0] = 111 (see Table 9) and Y[5:0] = 101000 (see Table 10),
yielding the following:
fREF = 26 MHz
fOUT1 = 625 × (66/64) MHz
1. Determine the output divide factor (ODF).
Note that the VCO frequency (fVCO) spans 3350 MHz to
4050 MHz. The ratio, fVCO/fOUT1, indicates the required ODF.
Given the specified value of fOUT1 (~644.53 MHz) and the
range of fVCO, the ODF spans a range of 5.2 to 6.3. The ODF
must be an integer, which means that ODF = 6 (because 6
is the only integer between 5.2 and 6.3).
2. Determine suitable values for P0 and P1.
The ODF is the product of the two output dividers, so
ODF = P0P1. It has already been determined that ODF = 6
for the given example. Therefore, P0P1 = 6 with the constraints
that P0 and P1 are both integers and that 4 ≤ P0 ≤ 11 (see
the Output/Input Frequency Relationship section). These
constraints lead to the single solution: P0 = 6 and P1 = 1.
Although this particular example yields a single solution
for the output divider values with fOUT1 ≈ 644.53 MHz, some
fOUT1 frequencies result in multiple ODFs rather than just
one. For example, if fOUT1 = 100 MHz the ODF ranges from
34 to 40. This leads to an assortment of possible values for
P0 and P1, as shown in Table 12.
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